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RTL Verification Engineer # 26-23383

U.S. Tech Solutions Inc.

Markham, Ontario • 3d ago

Easy Apply

Contract

$80 - $100

Sr. ASIC/SoC Design verification Engineer

Mavensoft Technologies, LLC

Remote • 11d ago

Easy Apply

Contract

120 - 127

Division Reliability Engineer

Greif, Inc.

Remote or Auburn, Washington • Today

Full-time

USD 129,500.00 - 220,500.00 per year

Job Details

Skills

VERIFICATION
DESIGN VERIFICATION
DESIGN-VERIFICATION
SYSTEMVERILOG
SYSTEM VERILOG
VERILOG
UVM
UNIVERSAL VERIFICATION METHODOLOGY

Summary

Duration: 8 months
Description:
As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs.
You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market.
The ideal candidate is passionate about verification methodologies, possesses strong expertise in System Verilog/UVM-based verification environments, and has hands-on experience with formal verification, functional coverage planning, and coverage-driven verification. This individual will thrive in a collaborative environment and enjoy solving complex technical challenges across all phases of product development.
Key Responsibilities

Define and execute comprehensive verification strategies for complex IP and subsystem designs.
Develop verification plans based on architecture and design specifications.
Design, implement, and maintain scalable SystemVerilog/UVM testbenches and reusable verification components.
Create directed and constrained-random test scenarios to validate functionality, performance, and robustness.
Develop functional coverage plans and coverage models, and drive coverage closure.
Define verification signoff criteria using simulation, functional coverage, assertion coverage, and formal verification metrics.
Apply formal verification methodologies including property checking, assertion development, protocol verification, and design correctness analysis.
Develop and maintain assertion-based verification (SVA) infrastructure and verification content.
Perform debugging and root-cause analysis of simulation, formal verification, and silicon issues.
Collaborate closely with architects, RTL designers, firmware, software, and validation teams throughout the product lifecycle.
Analyze verification metrics and recommend improvements to verification quality and efficiency.
Contribute to verification methodology development, automation, and continuous process improvement.

Preferred Experience

8-10 years of experience in ASIC, IP, or SoC verification.
Strong expertise in SystemVerilog, UVM, and constrained-random verification methodologies.
Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure.
Hands-on experience with formal verification methodologies and industry-standard formal verification tools.
Strong understanding of assertion-based verification (SVA) and formal property development.
Experience creating reusable verification environments, verification IP, and verification infrastructure.
Solid understanding of digital design concepts, computer architecture, and hardware verification methodologies.
Experience with simulation, regression management, coverage analysis, and debug tools.
Experience working through multiple successful silicon product cycles.
Strong communication and collaboration skills.

Preferred Technical Skills
Experience in one or more of the following areas is considered an asset:

Display IP and display subsystem verification
Formal verification and assertion-based verification (ABV)
Functional coverage architecture and coverage closure methodologies
Graphics, multimedia, and video processing pipelines
Display interfaces and protocols including DisplayPort, eDP, HDMI, and MIPI
High-speed interfaces and protocols
Memory subsystem verification

Academic Credentials

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Master's degree preferred.

What You'll Bring

Strong problem-solving and analytical skills.
Ability to work independently and drive technical initiatives.
Excellent verbal and written communication skills.
Experience leading verification efforts from planning through signoff.
Commitment to engineering excellence and product quality.
Passion to learn and adopt emerging technologies, including AI-assisted engineering tools, to enhance development efficiency and innovation.

About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

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#LI-AS140

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: usts
Position Id: 26-23383
Posted 3 days ago

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Remote

•

11d ago

Tittle : Sr. ASIC/SoC Design verification Engineer Work Location:Fully remote Duration:8 months Terms:W2 Contract Authorized US Worker- s Key Skills: Application-Specific Integrated Circuit (ASIC), System-on-Chip (SoC), SystemVerilog and UVM (Universal Verification Methodology) Position Summary: As aSenior Verification Engineeron the ASIC & Networking team, you support clients first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital beamformer with fir

Easy Apply

Contract

120 - 127

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

6d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

Easy Apply

Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

6d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

Easy Apply

Contract

Depends on Experience

DV CAD Engineer

Remote or California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a CAD Engineer focusing on the methodology and support of RTL design verification, you will work with architecture, design, software and verification leads to develop technology critical to the development of our products. You will be involved from conception to final creation and every step along the way. Roles and Responsibilities Work with chip leads to understand the

Full-time

USD 186,700.00 - 280,100.00 per year