OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Hardware Systems Engineering (CHSE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are seeking a Principal Optical Engineer to drive the architectural design, production roadmap, engineering efforts for next-generation optical interconnects in hyperscale AI infrastructure.
This role will serve as an architect/engineer responsible for Cloud/AI optical interconnects, and rack-scale fiber management. The candidate will work across silicon, systems, networking, platform architecture, datacenter engineering, and external ecosystem partners to bring innovative optical technologies from concept through large-scale production deployment.
The ideal candidate combines deep expertise in optical systems with architecture, ecosystem, and execution skills, and can influence platform-level decisions across multiple generations of AI infrastructure.
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ResponsibilitiesThis individual will serve as a technical leader for near-package optics (NPO), co-packaged optics (CPO), silicon photonics, and advanced packaging. The role will define multi-generation architectures and guide technologies from early feasibility through qualification, manufacturing ramp, and deployment in hyperscale AI systems.
- Own the end-to-end architecture and multi-generation roadmap for NPO and CPO optical interconnects used in AI scale-up networks.
- Translate system and network requirements into specifications for bandwidth density, reach, latency, energy per bit, optical-link budget, signal integrity, thermal limits, reliability, serviceability, manufacturability, and cost.
- Define silicon-photonic subsystem architectures, including optical engines, modulators, photodetectors, laser-source strategies, coupling interfaces, fiber attach, electronic-photonic integration, and control and monitoring functions.
- Build system models and budgets that connect photonic-device performance, SerDes and electrical channels, package parasitics, thermal behavior, controls, and network-level performance.
- Provide hands-on technical leadership in laboratory characterization and debug, including optical and electrical measurements, link bring-up, design-of-experiments, margin analysis, failure analysis, and correlation of simulation with measured data.
- Define verification, qualification, reliability, and manufacturing-test strategies at wafer, die, package, module, board, rack, and system levels
- Guide proof-of-concept designs through product definition, design reviews, qualification, manufacturing readiness, supply-chain ramp, and fleet deployment; lead root-cause and corrective-action efforts when issues arise.
- Drive technical alignment across silicon, packaging, signal integrity, thermal, mechanical, firmware, networking, manufacturing, and reliability teams.
- Set technical direction with foundries, OSATs, component suppliers, equipment vendors, and strategic partners; assess technology readiness, supply continuity, cost, yield, and roadmap alignment.
- Influence industry standards and ecosystem roadmaps, mentor engineers, and communicate complex architectural decisions and risks to technical and business leadership.
QualificationsRequired Qualifications: - Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR equivalent experience.
Other Requirements: - Ability to meet Microsoft, customer, and/or government security screening requirements is required for this role. These requirements include, but are not limited to, the following specialized security screening:
- Microsoft Cloud Background Check. This position is required to pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications: - Technical experience architecting or developing silicon photonics, VCSELs, optical engines, NPO, CPO, or closely related optical interconnects products.
- Hands-on laboratory experience characterizing and debugging photonic devices, optical links, or integrated optical modules using relevant optical and high-speed electrical test equipment and data-analysis methods.
- Experience leading architecture or product development across multiple disciplines and phases of the lifecycle, with demonstrated ownership of requirements, design tradeoffs, technical reviews, validation, and issue resolution.
- Experience communicating technical decisions, risks, and recommendations to cross-functional engineering teams, suppliers, and stakeholders.
- Doctorate Degree in Electrical Engineering, Optical Engineering, Photonics, Applied Physics, Materials Science, Mechanical Engineering, or related field AND 8+ years of technical engineering experience OR Master's Degree in a related field AND 10+ years of technical engineering experience OR Bachelor's Degree in a related field AND 14+ years of technical engineering experience OR equivalent experience.
- Demonstrated ownership of NPO, CPO, or optical I/O from concept through productization or production deployment.
- Experience with advanced photonic or semiconductor packaging, including optical coupling and fiber attach, electrical interfaces, thermal design, mechanical tolerances, assembly processes, and package-level test considerations.
- Deep knowledge of silicon photonic components and integration, including modulators (MRM or MZM), photodetectors, waveguides, couplers, multiplexers, laser integration, process variation, wafer-level test, and photonic design-kit constraints.
- Expertise in heterogeneous integration and advanced packaging technologies such as chiplets, interposers, 2.5D/3D integration, flip-chip, hybrid bonding, high-density substrates, fine-pitch assembly, and co-design of optical, electrical, thermal, and mechanical interfaces.
- Experience with driver/TIA, package and board signal integrity, and end-to-end link-budget and power modeling.
- Experience defining DFT, wafer and package test, screening, qualification, reliability, failure-analysis, and high-volume manufacturing strategies for photonic or semiconductor products.
- Experience with AI infrastructure, GPU or accelerator fabrics, Ethernet, InfiniBand, UALink, NVLink or other high-bandwidth scale-up and scale-out interconnect ecosystems.
- Experience working with silicon foundries, photonics foundries, OSATs, laser suppliers, fiber-attach and connector vendors, and contract manufacturers to drive roadmap, yield, cost, and supply-chain readiness.
- Record of technical influence through standards bodies, industry consortia, patents, publications, or delivery of differentiated commercial products.
Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
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This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about
requesting accommodations. 
