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Job Title: DFT Engineers (5 Positions) Location: Santa Clara, CA Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid und
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Contract, Third Party
Depends on Experience























