Job Title:
DFT MBIST Staff Engineer – Synopsys SMS | VCS | VecGen
Job Type: Contract – Corp to Corp (C2C)
Location: Remote – PST Time Zone
Rate: $90/hr C2C — flexible for the right candidate
Visa: Open to all work authorization types, subject to applicable employment requirements.
Duration: Contract
Job Description:
We are seeking a highly experienced DFT MBIST Staff Engineer to join our SoC Design-for-Test (DFT) team. This is a hands-on role focused on Memory BIST (MBIST) implementation, verification, simulation, pattern generation, and silicon bring-up.
The ideal candidate will have strong experience with Synopsys MBIST/SMS, VCS, and VecGen and should be able to independently own the MBIST flow from insertion through verification and post-silicon debug.
Key Responsibilities:
- Perform MBIST insertion for complex SoC designs using Synopsys SMS.
- Integrate and verify MBIST at the top level.
- Develop and debug MBIST simulations using Synopsys VCS.
- Work with RTL, no-delay gate-level, and timing-aware/with-delay simulations.
- Generate and validate MBIST patterns using VecGen.
- Debug RTL, simulation, and MBIST integration issues.
- Support silicon bring-up, characterization, and post-silicon debug.
- Troubleshoot memory failures and MBIST/DFT infrastructure issues.
- Work closely with DFT, RTL, Physical Design, and Product Engineering teams.
- Independently drive root-cause analysis and issue resolution.
Required Skills & Experience:
- 8+ years of hands-on DFT experience, with significant MBIST experience.
- Strong experience with Synopsys MBIST / SMS5 / SMS6.
- Strong experience with Synopsys VCS.
- Hands-on experience with VecGen pattern generation.
- Strong understanding of the complete MBIST flow:
- MBIST insertion
- Top-level integration
- Verification
- Pattern generation
- Diagnostics
- Simulation and debug
- Strong knowledge of March algorithms and memory test methodologies.
- Experience with BIRA/BISR, redundancy analysis, and memory repair.
- Experience debugging no-delay and with-delay simulations.
- Experience with silicon bring-up and post-silicon debug.
- Strong RTL/debugging skills with Verilog/SystemVerilog.
- Experience working with large and complex SoC designs containing multiple memory instances.
- Ability to work independently with minimal supervision.
Preferred Skills:
- Advanced SoC DFT integration.
- ATPG and scan insertion experience.
- Tcl, Perl, or Python scripting.
- Semiconductor product development experience.
- Strong communication and problem-solving skills.
Top Keywords:
MBIST | DFT | Synopsys SMS | SMS5 | SMS6 | VCS | VecGen | BIRA | BISR | Memory BIST | MBIST Insertion | MBIST Verification | March Algorithms | Memory Repair | DFT Integration | Silicon Bring-up | Post-Silicon Debug | Verilog | SystemVerilog | Tcl | Perl | Python
Recommended Dice screening questions
I would add these as Yes/No or short-answer questions:
- Do you have 8+ years of hands-on DFT experience?
- Do you have hands-on experience with Synopsys SMS5 or SMS6?
- Do you have hands-on MBIST insertion experience?
- Do you have experience with Synopsys VCS for MBIST verification?
- Do you have experience with VecGen?
- Do you have experience with BIRA/BISR and memory repair?
- Have you worked on no-delay and with-delay gate-level simulations?
- Do you have silicon bring-up/post-silicon MBIST debug experience?
- Are you available to work PST hours?
- Are you able to work on C2C?
One important change: I would avoid putting “Any Visa” in the public Dice posting. Dice specifically cautions employers against discriminatory job-posting language around citizenship/immigration status. Instead, screen candidates based on their legal ability to work under the engagement structure.
For a hard-to-fill role like this, after posting you can also use Dice's Invite to Apply feature to directly invite matching MBIST/DFT candidates.
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