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MBIST Staff Engineer

AIT Global, Inc.

Remote • Today

Easy Apply

Third Party, Contract

Senior MBIST Engineer

Apex Bridge Talent Group INC

Remote • 10d ago

Easy Apply

Contract, Third Party

Depends on Experience

Staff/Principal Engineer - HBM Design for Test (DFT)

Micron Technology, Inc.

Richardson, Texas • Today

Full-time

Staff Design Engineer, HBM

Micron Technology Inc

Richardson, Texas • Today

Full-time

Staff Test Engineer - Technology & Solutions

Infineon Technologies

San Jose, California • Today

Full-time

USD 117,900.00 per year

Sr. Staff Engineer - DFT

Ambiq Micro, Inc.

Austin, Texas • Today

Full-time

Senior Staff Test Engineer - Technology & Solutions

Infineon Technologies

San Jose, California • Today

Full-time

USD 147,400.00 per year

ASIC DFT Staff Engineer

AIT Global, Inc.

Remote • Today

Easy Apply

Contract, Third Party

Staff SoC DFT Engineer, HBM

Micron Technology, Inc.

Richardson, Texas • Today

Full-time

USD 146,000.00 - 247,000.00 per year

DFT Engineer (Design for Testability) - Staff

Micron Technology, Inc.

Richardson, Texas • Today

Full-time

DFT Staff Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 145,600.00 per year

Job Details

Skills

python
Perl
MBIST

Summary

Job Title: MBIST Staff Engineer
Location: Remote

Position Summary:

We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.

Responsibilities:

Perform MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST at the top level.
Develop, execute, and debug MBIST simulations using Synopsys VCS, including:
RTL
No-delay gate level simulations
With-delay (timing-aware) simulations
Generate and validate MBIST test patterns using Vecgen.
Debug RTL, simulation, and MBIST integration issues.
Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure.
Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.
Drive issue resolution independently and document implementation flows and debug findings.

Required Qualifications:

8+ years of hands-on DFT experience, with significant focus on MBIST.
Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.
Proficiency with Synopsys VCS for MBIST verification and simulation.
Deep understanding of the complete MBIST flow:
MBIST insertion
Top-level integration
Verification
Pattern generation (Vecgen)
Diagnostics
Simulation and debug
Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).

Experience running and debugging:

No-delay simulations
With-delay simulations
Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
Strong debugging and root-cause analysis skills across RTL, MBIST, and simulation environments.
Ability to work independently with minimal supervision.
Experience with large, complex SoC designs containing multiple memory instances.
Familiarity with Verilog/SystemVerilog and standard DFT methodologies.

Preferred Qualifications:

Experience with advanced SoC DFT integration.
Familiarity with ATPG and scan insertion flows.
Experience with scripting (Tcl, Perl, or Python) to automate MBIST flows and debug.
Experience working in fast-paced semiconductor product development.

Key Skills:

Synopsys MBIST (SMS5/SMS6)
Synopsys VCS
MBIST insertion
Top-level MBIST verification
VecGen pattern generation
MBIST diagnostics
MBIST repair schemes and memory test algorithms
No-delay, with-delay simulation and debug
Silicon bring-up and post-silicon debug
SoC DFT integration
Tcl / Perl / Python scripting
Strong communication skills
Self-motivated and capable of working independently

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10106248
Position Id: 2026-4375
Posted 9 hours ago

Fitment

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Similar Jobs

Senior MBIST Engineer

Remote

•

10d ago

Business Title: Senior MBIST Engineer Location: California Job Type: Contract Note: Remote, must be working as per PST time zone Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

18d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Third Party, Contract

110 - 120

ASIC DFT Staff Engineer

Remote

•

Today

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

Easy Apply

Contract, Third Party

Asics Engineer

Remote

•

Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Job Details

Skills

python
Perl
MBIST

Summary

Job Title: MBIST Staff Engineer
Location: Remote

Position Summary:

Responsibilities:

Perform MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST at the top level.
Develop, execute, and debug MBIST simulations using Synopsys VCS, including:
RTL
No-delay gate level simulations
With-delay (timing-aware) simulations
Generate and validate MBIST test patterns using Vecgen.
Debug RTL, simulation, and MBIST integration issues.
Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure.
Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.
Drive issue resolution independently and document implementation flows and debug findings.

Required Qualifications:

8+ years of hands-on DFT experience, with significant focus on MBIST.
Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.
Proficiency with Synopsys VCS for MBIST verification and simulation.
Deep understanding of the complete MBIST flow:
MBIST insertion
Top-level integration
Verification
Pattern generation (Vecgen)
Diagnostics
Simulation and debug
Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).

Experience running and debugging:

No-delay simulations
With-delay simulations
Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
Strong debugging and root-cause analysis skills across RTL, MBIST, and simulation environments.
Ability to work independently with minimal supervision.
Experience with large, complex SoC designs containing multiple memory instances.
Familiarity with Verilog/SystemVerilog and standard DFT methodologies.

Preferred Qualifications:

Experience with advanced SoC DFT integration.
Familiarity with ATPG and scan insertion flows.
Experience with scripting (Tcl, Perl, or Python) to automate MBIST flows and debug.
Experience working in fast-paced semiconductor product development.

Key Skills:

Synopsys MBIST (SMS5/SMS6)
Synopsys VCS
MBIST insertion
Top-level MBIST verification
VecGen pattern generation
MBIST diagnostics
MBIST repair schemes and memory test algorithms
No-delay, with-delay simulation and debug
Silicon bring-up and post-silicon debug
SoC DFT integration
Tcl / Perl / Python scripting
Strong communication skills
Self-motivated and capable of working independently

Dice Id: 10106248
Position Id: 2026-4375
Posted 9 hours ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Senior MBIST Engineer

Remote

•

10d ago

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

18d ago

Easy Apply

Third Party, Contract

110 - 120

ASIC DFT Staff Engineer

Remote

•

Today

Easy Apply

Contract, Third Party

Asics Engineer

Remote

•

Today

Full-time