Remote
•
Today
RTL Power Optimization, Clock gating, Data gating, Experience with Front-end tools like RTL Architect, Power Artist
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Contract
Depends on Experience
18700 results (821 new)


Qualcomm
Santa Clara, California • Today
Full-time
Compensation information provided in the description





FSTONE Technologies
Hybrid in Sunnyvale, California • Today
Easy Apply
Contract, Third Party
Depends on Experience

Balin Technologies LLC
San Jose, California • Today
Easy Apply
Third Party, Contract
Depends on Experience





Comprehensive Resources Inc.
Sunnyvale, California • Today
Easy Apply
Full-time, Part-time, Contract, Third Party










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Remote
•
11d ago
This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Job Title : SoC / RTL Integration Engineer Location : Remote Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using Verilog/system Verilog, synthesis, timing constraints,
Easy Apply
Contract
70 - 75
Remote or California
•
Today
Position: SOC/IP Integration Engineer (eInfochips) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital conceptsSubsystem or SoC integrationIntegration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration.Ensure customer satisfaction.Rep
Full-time
Remote or California
•
Today
Position: SOC/IP Integration Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital conceptsSubsystem or SoC integrationIntegration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration.Ensure customer satisfaction
Full-time