Job Title: Sr. Advanced Package Design Engineer
Location: San Diego, CA – Onsite
Duration: 12 months with potential for extension may be available based on project needs
Target Start Date: ASAP / based on candidate availability
Job Description:
We are seeking a Sr Advanced Package Design Engineer with deep experience in semiconductor physical design, layout, and production tapeout. This individual will support the development of high-performance semiconductor designs and advanced packaging solutions from physical implementation through final foundry release.
The ideal candidate has personally completed tapeouts with a major semiconductor foundry and has hands-on experience performing layout or physical implementation at the die, design-block, interposer, or package level. Experience with advanced package technologies such as silicon interposers, RDL fan-out, silicon bridges, or 2.5D/3D integration is highly relevant.
Key Responsibilities:
Own and support semiconductor physical layout and design activities through tapeout, including resolving implementation issues and ensuring designs are ready for foundry release. Apply hands-on knowledge of physical-design and package-layout tools to support block, die, interposer, and advanced-package development.
Required Experience:
10+ years of semiconductor physical design, package design, layout, or closely related experience
Direct experience taking semiconductor designs through production tapeout at a major foundry, such as TSMC, Samsung, Intel Foundry, GlobalFoundries, or similar
Hands-on layout / physical implementation experience at the die, design-block, interposer, substrate, or package level
Experience with semiconductor physical-design or package-layout tools such as Synopsys ICC2, Synopsys Custom Compiler, Cadence APD, or comparable platforms
Preferred / Standout Experience:
Advanced packaging experience involving silicon interposers, RDL fan-out, silicon bridges, chiplets, or 2.5D/3D integration
Experience with package electrical analysis, signal integrity / power integrity, or 3D electromagnetic analysis such as Ansys HFSS
Multiple successful tapeouts across advanced semiconductor processes or complex high-speed designs
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