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Design for Testability (DFT) Engineer

Info Way Solutions

San Francisco, California • 2d ago

Easy Apply

Full-time

Depends on Experience

Job Details

Skills

2.5D
3D Computer Graphics
ASIC
ATPG
Art
Artificial Intelligence
Automated Testing
Bash
Cadence
Collaboration
Computer Engineering
Computer Hardware
Computer Networking
DFT
Data Analysis
Data Compression
Debugging
EDA
Electrical Engineering
Failure Analysis
ISO 9000
JTAG
MBIST
Mentorship
Perl
Physical Data Model
Pure Data
Python
Quality Assurance
SDF
Scripting
Semiconductors
Shell
Siemens
Software Development
Static Timing Analysis
Synopsys
System On A Chip
SystemVerilog
Tcl
Tk
Translation
VHDL
Verilog
Workflow

2.5D
3D Computer Graphics
ASIC
ATPG
Art
Artificial Intelligence
Automated Testing
Bash
Cadence
Collaboration
Computer Engineering
Computer Hardware
Computer Networking
DFT
Data Analysis
Data Compression
Debugging
EDA
Electrical Engineering
Failure Analysis
ISO 9000
JTAG
MBIST
Mentorship
Perl
Physical Data Model
Pure Data
Python
Quality Assurance
SDF
Scripting
Semiconductors
Shell
Siemens
Software Development
Static Timing Analysis
Synopsys
System On A Chip
SystemVerilog
Tcl
Tk
Translation
VHDL
Verilog
Workflow

Summary

About the Role

L&T Technology Services (LTTS) is looking for talented, hands-on DFT Engineers to join our semiconductor engineering team in the Bay Area, CA. In this role, you will work on cutting-edge, complex SoCs targeting AI, Automotive, Networking, and Next-Gen Compute applications. You will be responsible for defining, implementing, and verifying state-of-the-art DFT architectures across advanced technology nodes.

Key Responsibilities

DFT Architecture & Implementation: Implement and verify Scan, Compression, ATPG, MBIST, LBIST, and IEEE standards (1149.1 JTAG, 1500, 1687 IJTAG, 21686).
ATPG & Fault Coverage: Generate, debug, and optimize ATPG patterns (Stuck-at, At-Speed / Transition, Cell-Aware, Path Delay) to achieve high fault coverage metrics.
Memory BIST & Logic BIST: Insert and verify MBIST/LBIST controllers across complex multi-frequency clock domains and multi-die / chiplet architectures.
Simulation & Timing Verification: Perform zero-delay and timing-annotated (SDF) pattern simulations, debug timing violations, and collaborate with Physical Design (PD) teams on DFT constraints and STA closure.
Silicon Bring-up & ATE Support: Assist product and test engineering teams during silicon bring-up, pattern translation (WGL/STIL), and failure analysis on Automated Test Equipment (ATE).

Required Qualifications & Skills

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
Experience: 3+ years of hands-on DFT implementation and verification experience on complex ASIC/SoC designs.
EDA Tool Expertise: Strong proficiency in at least one major EDA vendor DFT suite:
- Siemens/Mentor: Tessent (Tessent Scan, FastScan, TK/TestKompress, Tessent Shell, IJTAG, MemoryBIST).
- Synopsys: TestMAX (DFTMAX, TetraMAX, SMS/MBIST).
- Cadence: Modus DFT Software.
Programming/Scripting: Hands-on experience with TCL, Perl, Python, or Bash for flow automation.
Hardware Description Languages: Proficient in Verilog, SystemVerilog, and VHDL.

Preferred / Plus Skills

Experience with advanced nodes (5nm, 3nm, 2nm) and multi-die / 2.5D / 3D chiplet architectures.
Hands-on experience with Silicon Bring-Up and ATE pattern validation in a lab/test house environment.
Deep understanding of Fault Diagnostics and yield learning workflows.
Familiarity with Automotive Safety standards (ISO 26262) and functional safety (FuSa) DFT mechanisms.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 90769335A
Position Id: 9102435
Posted 2 days ago

Fitment

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Contact the job poster

Girish Tanwar

Recruiter @ Info Way Solutions

View Profile

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Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

Engineering Intern - Design-for-Test (Spring 2027 Co-Op)

Palo Alto, California

•

Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

USD 45.00 - 51.00 per hour

CPU DFT Engineer

Santa Clara, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to

Full-time

USD 142,200.00 - 213,400.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Job Details

Skills

2.5D
3D Computer Graphics
ASIC
ATPG
Art
Artificial Intelligence
Automated Testing
Bash
Cadence
Collaboration
Computer Engineering
Computer Hardware
Computer Networking
DFT
Data Analysis
Data Compression
Debugging
EDA
Electrical Engineering
Failure Analysis
ISO 9000
JTAG
MBIST
Mentorship
Perl
Physical Data Model
Pure Data
Python
Quality Assurance
SDF
Scripting
Semiconductors
Shell
Siemens
Software Development
Static Timing Analysis
Synopsys
System On A Chip
SystemVerilog
Tcl
Tk
Translation
VHDL
Verilog
Workflow

2.5D
3D Computer Graphics
ASIC
ATPG
Art
Artificial Intelligence
Automated Testing
Bash
Cadence
Collaboration
Computer Engineering
Computer Hardware
Computer Networking
DFT
Data Analysis
Data Compression
Debugging
EDA
Electrical Engineering
Failure Analysis
ISO 9000
JTAG
MBIST
Mentorship
Perl
Physical Data Model
Pure Data
Python
Quality Assurance
SDF
Scripting
Semiconductors
Shell
Siemens
Software Development
Static Timing Analysis
Synopsys
System On A Chip
SystemVerilog
Tcl
Tk
Translation
VHDL
Verilog
Workflow

Summary

About the Role

Key Responsibilities

DFT Architecture & Implementation: Implement and verify Scan, Compression, ATPG, MBIST, LBIST, and IEEE standards (1149.1 JTAG, 1500, 1687 IJTAG, 21686).
ATPG & Fault Coverage: Generate, debug, and optimize ATPG patterns (Stuck-at, At-Speed / Transition, Cell-Aware, Path Delay) to achieve high fault coverage metrics.
Memory BIST & Logic BIST: Insert and verify MBIST/LBIST controllers across complex multi-frequency clock domains and multi-die / chiplet architectures.
Simulation & Timing Verification: Perform zero-delay and timing-annotated (SDF) pattern simulations, debug timing violations, and collaborate with Physical Design (PD) teams on DFT constraints and STA closure.
Silicon Bring-up & ATE Support: Assist product and test engineering teams during silicon bring-up, pattern translation (WGL/STIL), and failure analysis on Automated Test Equipment (ATE).

Required Qualifications & Skills

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
Experience: 3+ years of hands-on DFT implementation and verification experience on complex ASIC/SoC designs.
EDA Tool Expertise: Strong proficiency in at least one major EDA vendor DFT suite:
- Siemens/Mentor: Tessent (Tessent Scan, FastScan, TK/TestKompress, Tessent Shell, IJTAG, MemoryBIST).
- Synopsys: TestMAX (DFTMAX, TetraMAX, SMS/MBIST).
- Cadence: Modus DFT Software.
Programming/Scripting: Hands-on experience with TCL, Perl, Python, or Bash for flow automation.
Hardware Description Languages: Proficient in Verilog, SystemVerilog, and VHDL.

Preferred / Plus Skills

Experience with advanced nodes (5nm, 3nm, 2nm) and multi-die / 2.5D / 3D chiplet architectures.
Hands-on experience with Silicon Bring-Up and ATE pattern validation in a lab/test house environment.
Deep understanding of Fault Diagnostics and yield learning workflows.
Familiarity with Automotive Safety standards (ISO 26262) and functional safety (FuSa) DFT mechanisms.

Dice Id: 90769335A
Position Id: 9102435
Posted 2 days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Contact the job poster

Girish Tanwar

Recruiter @ Info Way Solutions

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Palo Alto, California

•

Today

Full-time

USD 220,000.00 - 355,000.00 per year

Engineering Intern - Design-for-Test (Spring 2027 Co-Op)

Palo Alto, California

•

Today

Full-time

USD 45.00 - 51.00 per hour

CPU DFT Engineer

Santa Clara, California

•

Today

Full-time

USD 142,200.00 - 213,400.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Design for Testability (DFT) Engineer

Skills

Summary

About the Role

Key Responsibilities

Required Qualifications & Skills

Preferred / Plus Skills

Dice Job Match Score™

Girish Tanwar

Similar Jobs

Design for Testability (DFT) Engineer

Job Details

Skills

Summary

About the Role

Key Responsibilities

Required Qualifications & Skills

Preferred / Plus Skills

Dice Job Match Score™

Girish Tanwar

Similar Jobs