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Lead Functional Product Engineer, Power Analysis

Cadence Design Systems Inc

San Jose, California • Today

Full-time

USD 114,800.00 - 213,200.00 per year

Lead Product Engineer

Cadence Design Systems Inc

San Jose, California • Today

Full-time

USD 114,800.00 - 213,200.00 per year

Lead Software Engineer - Low Power Verification

Cadence Design Systems Inc

San Jose, California • Today

Full-time

USD 114,800.00 - 213,200.00 per year

Product Design Engineering Lead - Beats

Apple, Inc.

Cupertino, California • Yesterday

Full-time

Lead Engineer - Product Catalog Team

Stitch Fix

Remote • Today

Full-time

USD 125,000.00 - 186,000.00 per year

Lead Product Owner - Data Analytics

Ferguson Enterprises, LLC

Remote or Springfield, Virginia • Today

Full-time

USD 8,470.59 - 14,834.37 per month

PowerApps Technical Lead

ITCON Services

Remote or Hybrid in Tysons, Virginia • 16d ago

Easy Apply

Full-time

150,000 - 160000

Data Engineering Lead

Deckers Brands

Remote or California • Today

Full-time

USD 122,300.00 - 165,000.00 per year

Lead CPU Performance Analysis Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 272,900.00 - 409,300.00 per year

Technical Lead Power Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 160,000.00 per year

Lead Engineer

Green Dot Corporation

Remote or Los Angeles, California • Today

Full-time

USD 139,900.00 - 199,300.00 per year

Job Details

Skills

Cadence
Research and Development
Technical Support
Collaboration
Debugging
Optimization
Verilog
SystemVerilog
Design Analysis
Test Cases
Digital Design
Scripting
Tcl
Python
Shell
Electronics
VLSI
Computer Engineering
Sales

Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments.

Key Responsibilities

Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages
Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
Deploy and validate power analysis tools at customer sites; provide hands-on technical support
Collaborate with customers to optimize power results and improve flow efficiency
Contribute to flow automation and scripting for repeatable deployments
Document debug findings, best practices, and flow guidelines

Required Skills

Hands-on experience with Signoff power analysis (static and dynamic power)
Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection,
Working knowledge of UPF (Unified Power Format) - power domains, isolation, level shifting, retention
Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
Understanding of digital design fundamentals - clock domains, pipeline stages, timing/power trade-offs
Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
Familiarity with Liberty (.lib) and SPEF formats
Scripting skills: Tcl, Python, or Shell
Familiarity with tools such as Joules, Voltus, PTPX or equivalent

Education & Experience

B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
Must have 3+ years of industry work experience

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: CADENCE
Position Id: d1b9503f6bce8e0ca148a3e628d978de
Posted 30+ days ago

Fitment

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This Senior Principal Product Engineer is a technical leader on the Voltus product engineering team, working on Cadence's power noise and reliability analysis platform. The role sits between strategic customers/foundries, Applications, and R&D, and is accountable for turning the hardest IR/EM, PDN, and electrothermal signoff requirements into product and flow solutions. Key responsibil

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Job Details

Skills

Cadence
Research and Development
Technical Support
Collaboration
Debugging
Optimization
Verilog
SystemVerilog
Design Analysis
Test Cases
Digital Design
Scripting
Tcl
Python
Shell
Electronics
VLSI
Computer Engineering
Sales

Summary

Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages
Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
Deploy and validate power analysis tools at customer sites; provide hands-on technical support
Collaborate with customers to optimize power results and improve flow efficiency
Contribute to flow automation and scripting for repeatable deployments
Document debug findings, best practices, and flow guidelines

Required Skills

Hands-on experience with Signoff power analysis (static and dynamic power)
Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection,
Working knowledge of UPF (Unified Power Format) - power domains, isolation, level shifting, retention
Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
Understanding of digital design fundamentals - clock domains, pipeline stages, timing/power trade-offs
Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
Familiarity with Liberty (.lib) and SPEF formats
Scripting skills: Tcl, Python, or Shell
Familiarity with tools such as Joules, Voltus, PTPX or equivalent

Education & Experience

B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
Must have 3+ years of industry work experience

Dice Id: CADENCE
Position Id: d1b9503f6bce8e0ca148a3e628d978de
Posted 30+ days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Sr. Principal Product Engineer

San Jose, California

•

Today

Full-time

USD 161,000.00 - 299,000.00 per year

Physical Analysis Engineer

Cupertino, California

•

Yesterday

Full-time

USD 150,400.00 - 225,300.00 per year

Timing Engineer

San Jose, California

•

Today

Full-time

USD 118,900.00 - 172,000.00 per year

Signal Integrity Engineer

San Jose, California

•

Today

Full-time

USD 143,800.00 - 230,000.00 per year