Position: Senior RTL / STA Engineer
Location: San Jose, California (on-site preferred)
Duration:12+ months
No.of Positions: 1
Role Overview
Cisco’s ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows.
Key Responsibilities
Develop, review, debug, and verify timing constraints for ASIC designs.
Contribute to RTL design and collaborate with design, verification, synthesis, and DFT teams to resolve timing and implementation issues.
Analyze timing behavior and support timing closure across functional and test operating modes, including DFT modes where applicable.
Debug timing constraints and reports using industry-standard STA and synthesis tools.
Use scripting and automation to improve constraint checks, analysis, and engineering workflows.
Minimum Qualifications
Bachelor’s degree and 8 years of related experience, or Master’s degree and 6 years of related experience, or PhD and 3 years of related experience.
Prior hands-on experience developing and verifying timing constraints.
Prior hands-on experience with RTL design.
Programming experience with at least two of the following: Perl, Tcl, Python, or Makefile.
Preferred Qualifications
Master’s degree with 15+ years of experience.
Experience debugging and analyzing PCIe timing constraints and TSMC memory timing constraints.
Experience with RTL design, CDC/RDC, and Conformal verification.
Experience debugging and analyzing timing constraints and closing timing for DFT modes, including scan shift/capture and BIST.
Experience debugging SDC and using Synopsys TCM and PrimeTime STA tools.
Experience with Synopsys Fusion Compiler and Design Compiler synthesis tools.
Experience with Tessent, including DFT insertion in RTL.
