Immediate need for a talented Senior Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Jose, CA(Onsite). Please review the job description below and contact me ASAP if you are interested.
Job ID:26-19462
Pay Range: $150000 - $160000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Key Responsibilities:
- Design and develop reusable UVM-based verification environments, including UVM agents, scoreboards, checkers, monitors, and behavioral models.
- Create and execute randomized and directed test cases to achieve functional and code coverage goals.
- Develop and maintain SystemVerilog Assertions (SVA) for protocol and design verification.
- Verify complex digital and mixed-signal (MXS) IPs and SoCs at both block and system levels.
- Analyze and debug simulation failures at the RTL and gate-level, including working with gate-level netlists and SDF timing simulations.
- Collaborate with RTL designers to identify, isolate, and resolve design issues.
- Develop scalable and reusable verification architectures and methodologies.
- Utilize scripting languages such as Perl, Python, or Tcl for automation and regression management.
- Work with industry-standard EDA simulation tools from Synopsys, Cadence, and Siemens Mentor Graphics.
- Manage source code using Git or DesignSync.
- Participate in design reviews, verification planning, and coverage closure activities.
- Work effectively within global cross-functional engineering teams.
Key Requirements and Technology Experience:
- Must have skills: ASIC/SoC Design Verification, SystemVerilog, UVM, and SystemVerilog Assertions (SVA) and Synopsys, Cadence, and Mentor Graphics.
- Experience: 6 10+ Years
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of experience, or Master's degree with 6+ years of experience.
- 6+ years of experience in ASIC/SoC Design Verification.
- Strong expertise in SystemVerilog, UVM, and SystemVerilog Assertions (SVA).
- Experience verifying designs at both block and system levels.
- Experience with RTL, gate-level verification, netlists, and SDF timing simulations.
- Experience verifying mixed-signal circuits, including:
- PLL
- DLL
- ADC
- DAC
- Strong debugging skills involving RTL, gate-level simulations, and analog/mixed-signal schematic analysis.
- Hands-on experience with Synopsys, Cadence, and Mentor Graphics simulation tools.
- Experience with scripting languages such as Python, Perl, or Tcl.
- Experience with version control systems such as Git or DesignSync.
- Excellent analytical, communication, and problem-solving skills.
- Ability to work independently and within distributed global teams.
Our client is a leading IT Industry, and we are currently interviewing to fill this and other similar fulltime positions. If you are interested in this position, please apply online for immediate consideration.
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