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Validation Engineer 3 # 26-26845

U.S. Tech Solutions Inc.

San Jose, California • 6d ago

Easy Apply

Contract

$75 - $85

Validation Engineer 3

TPI Global (formerly Tech Providers, Inc.)

San Jose, California • Today

Full-time

Firmware Validation Engineer - Brake & Steering

Comrise

Foster City, California • Today

Easy Apply

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$89

Senior Verification & Validation (V&V) Engineer

SysMind, LLC

Milpitas, California • Yesterday

Easy Apply

Third Party, Contract

$48 - $52

Embedded Systems Validation Test Engineer (Python)

OSI Engineering, Inc.

Cupertino, California • 9d ago

Easy Apply

Contract

72 - 92

Validation Engineer 4 – Processor / Silicon Validation

VGAI Solutions Inc

Hybrid in San Jose, California • 6d ago

Easy Apply

Contract

65 - 70

Hardware Validation Engineer

Metalight Solutions Inc

Fremont, California • Today

Easy Apply

Contract

Depends on Experience

Senior Verification & Validation (V&V) Engineer - W2 Only

ASCII Group LLC

Milpitas, California • Yesterday

Easy Apply

Contract

53+

Reliability Engineer/Architect (hardware validation)

Apetan Consulting

Milpitas, California • 13d ago

Easy Apply

Contract

Depends on Experience

Electrical Validation Engineer

SGS Consulting

Sunnyvale, California • 5d ago

Easy Apply

Contract

70 - 105

Application Validation Engineer

SUPERMICRO COMPUTER INC

San Jose, California • Today

Full-time

USD 90,000.00 - 105,000.00 per year

Hardware Validation Engineer

HCL America Inc.

Fremont, California • 15d ago

Easy Apply

Full-time

$57 - $59

Senior Verification & Validation (V&V) Engineer

Purple Drive Technologies LLC

Milpitas, California • Today

Easy Apply

Full-time, Part-time, Contract, Third Party

Senior System Validation Engineer

OSI Engineering, Inc.

Hybrid in Sunnyvale, California • 13d ago

Easy Apply

Contract

Depends on Experience

Staff Software Engineer, Validation Foundations and Acceleration

General Motors

Sunnyvale, California • Today

Full-time

USD 189,300.00 - 290,700.00 per year

Senior Software Systems Engineer, Autonomous Systems Validation Confidence

General Motors

Remote or Sunnyvale, California • Today

Full-time

USD 153,200.00 - 234,100.00 per year

Senior System Integration & Optical Validation Engineer

PsiQuantum

Milpitas, California • Today

Full-time

Software Verification & Validation Engineer

PlusAI

Santa Clara, California • Today

Full-time

USD 110,000.00 - 140,000.00 per year

Senior Electronics Systems Integration & Validation Engineer

PsiQuantum

Milpitas, California • Today

Full-time

Validation/Characterization Engineer

Texas Instruments Incorporated

Santa Clara, California • Today

Full-time

Validation Engineer - Onsite

VIVA USA INC

San Jose, California • Yesterday

Easy Apply

Contract

71 - 76

Principal Engineer - Validation Engineering

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 240,000.00 per year

Embedded Validation Engineer

Ace Technologies, Inc.

Sunnyvale, California • Today

Easy Apply

Contract, Third Party

Depends on Experience

Design Validation Engineer

ATEM Corp

San Jose, California • 15d ago

Easy Apply

Full-time

Depends on Experience

Validation Engineer

hyve solutions

Fremont, California • Today

Full-time

USD 110,000.00 - 180,000.00 per year

Platform Validation Engineer

Aziro Technologies LLC

Santa Clara, California • Yesterday

Easy Apply

Contract

65 - 75

Vehicle Validation Engineer EV Powertrain

Pi-Square Technologies

San Jose, California • Today

Full-time

USD 45.00 - 50.00 per hour

Principal Post-Silicon Validation Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 207,000.00 - 230,000.00 per year

Display Architecture Validation Engineer, Platform Architecture

Apple, Inc.

Cupertino, California • Today

Full-time

Staff System Validation Engineer

SUPERMICRO COMPUTER INC

San Jose, California • Today

Full-time

Job Details

Skills

TEST
TESTING
TESTED
VALIDATE
VALIDATION
VALIDATING
ATE
ADVANTEST
TERADYNE
ULTRAFLEX
ATPG
SCAN
BIST
MBIST
ENGINEER

Summary

Duration: 12-month contract

Job Description:

We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces.
This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability.
Strong understanding of SerDes and protocols such as UCIe and PCIe is required, with emphasis on translating characterization into robust, multisite production tests.
Experience with Python-based automation and data analytics is essential; familiarity with AI-assisted tools for test development and data triage is a plus.

Responsibilities:

Own development, integration, and maintenance of wafer sort and final test programs on ATE for SoC SerDes with copackaged optics.
Define and implement production test coverage for SerDes PHY and protocol features (PRBS, loopback, margining, FEC, CDR lock, EQ settings) using on-die BIST/DFT and ATE instrumentation.
Implement and optimize multisite strategies, parallel test execution, guardbanding, and test time reduction while meeting quality and coverage goals.
Correlate bench/char results to ATE: develop golden-unit flows, establish limits, build characterization-to-production handoff, and close gaps.
Integrate DFT features (scan/ATPG, boundary scan, MBIST/LBIST, JTAG) into production flows; manage pattern conversion, timing sets, and pin maps.
Implement UCIe/PCIe-related production checks: link training emulation, LTSSM state verification via firmware or test hooks, compliance counters, and error injection/monitoring.
Build Python-based tooling for ATE control, data parsing, STDF analytics, dashboards, and automated limit updates; integrate with MES/SPC and CI pipelines.
Collaborate with silicon design, firmware, DFT, product engineering, OSAT/probe, and SI teams to resolve issues and qualify ECOs/revisions.
Document test plans, specifications, vector maps, limits, and release notes; train operations teams and support sustaining engineering.

Experience:

Minimum 5 years’ of experience

Skillsets:

Hands-on experience developing on leading ATE platforms (e.g., Advantest V93K/AC+, Teradyne UltraFLEX/UltraFLEXplus) including timing sets, DC/AC measurements, and multisite.
Strong understanding of SerDes/PHY fundamentals: equalization, CDR, CTLE/DFE, PRBS/BER, margining, jitter/eye constraints, and on-die BIST integration.
Proficiency in Python for automation and data analytics; experience with STDF parsing, visualization, and automated SPC/anomaly detection.
Solid DFT background: scan/ATPG patterns, boundary scan, MBIST/LBIST, JTAG access, pattern formats (WGL/STIL), and pattern bring-up on ATE.
Working knowledge of UCIe and PCIe (Gen5/Gen6 preferred) from a production test perspective: link checks via firmware/test hooks, error counters, and compliance indicators.
Excellent documentation, cross-functional communication, and problem-solving skills.

Education:

Under-graduate degree preferred.

About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

#LI-AS140

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: usts
Position Id: 26-26845
Posted 6 days ago

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Job Details

Skills

TEST
TESTING
TESTED
VALIDATE
VALIDATION
VALIDATING
ATE
ADVANTEST
TERADYNE
ULTRAFLEX
ATPG
SCAN
BIST
MBIST
ENGINEER

Summary

Duration: 12-month contract

Job Description:

We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces.
This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability.
Strong understanding of SerDes and protocols such as UCIe and PCIe is required, with emphasis on translating characterization into robust, multisite production tests.
Experience with Python-based automation and data analytics is essential; familiarity with AI-assisted tools for test development and data triage is a plus.

Responsibilities:

Own development, integration, and maintenance of wafer sort and final test programs on ATE for SoC SerDes with copackaged optics.
Define and implement production test coverage for SerDes PHY and protocol features (PRBS, loopback, margining, FEC, CDR lock, EQ settings) using on-die BIST/DFT and ATE instrumentation.
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Correlate bench/char results to ATE: develop golden-unit flows, establish limits, build characterization-to-production handoff, and close gaps.
Integrate DFT features (scan/ATPG, boundary scan, MBIST/LBIST, JTAG) into production flows; manage pattern conversion, timing sets, and pin maps.
Implement UCIe/PCIe-related production checks: link training emulation, LTSSM state verification via firmware or test hooks, compliance counters, and error injection/monitoring.
Build Python-based tooling for ATE control, data parsing, STDF analytics, dashboards, and automated limit updates; integrate with MES/SPC and CI pipelines.
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Experience:

Minimum 5 years’ of experience

Skillsets:

Hands-on experience developing on leading ATE platforms (e.g., Advantest V93K/AC+, Teradyne UltraFLEX/UltraFLEXplus) including timing sets, DC/AC measurements, and multisite.
Strong understanding of SerDes/PHY fundamentals: equalization, CDR, CTLE/DFE, PRBS/BER, margining, jitter/eye constraints, and on-die BIST integration.
Proficiency in Python for automation and data analytics; experience with STDF parsing, visualization, and automated SPC/anomaly detection.
Solid DFT background: scan/ATPG patterns, boundary scan, MBIST/LBIST, JTAG access, pattern formats (WGL/STIL), and pattern bring-up on ATE.
Working knowledge of UCIe and PCIe (Gen5/Gen6 preferred) from a production test perspective: link checks via firmware/test hooks, error counters, and compliance indicators.
Excellent documentation, cross-functional communication, and problem-solving skills.

Education:

Under-graduate degree preferred.

Dice Id: usts
Position Id: 26-26845
Posted 6 days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

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Similar Jobs

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