Santa Clara, California
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Today
3+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) Experience with code and functional coverage analysis Proficient in debugging and problem-solving Scripting experience in Python or Perl Knowledge of Verilog and/or VHDL
Easy Apply
Full-time
Depends on Experience