Search Jobs | Dice.com

1 results (1 new)

Group by company

SoC Validation Engineer_ Pre & Post-Silicon

Tekfortune Inc.

Sunnyvale, California • Today

Easy Apply

Contract, Third Party

$70 - $77

Job Details

Skills

Automated Testing
Interfaces
Integrated Circuit
I2C
Root Cause Analysis
Verification And Validation

Summary

Role:                 SoC Validation Engineer_ Pre & Post-Silicon
Location:         Sunnyvale CA (Onsite)
 
 
Summary 

We are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems   including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs   with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production. 
 
 
Key Responsibilities 
 Pre-Silicon Validation

Develop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers), Reset Architecture, Ethernet MAC/PHY, and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)

Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level

Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior

Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces

Perform functional coverage analysis and drive coverage closure across IP blocks

Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews

Execute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integration

Post-Silicon Validation

Bring up and validate SoC IPs on first silicon and platform boards

Develop and execute post-silicon test plans covering:

Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions

Reset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection

Ethernet: Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping

I/O: Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing

Debug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx, and embedded trace tools

Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams

Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions

Develop and maintain automated test frameworks for regression and production testing

Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug

General

Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases

Develop Python/Perl/Tcl scripts for test automation, log parsing, and result analysis

Participate in silicon bring-up triage, failure analysis, and bug review meetings

Mentor junior engineers and drive process improvements in validation methodology

Interface with IP vendors for third-party IP integration, compliance, and issue resolution

 
Required Qualifications

Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field

Experience: 4 10+ years in SoC validation (pre-silicon and/or post-silicon)

Deep understanding of SoC architecture and IP integration concepts

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 90941404
Position Id: LAKSJDppp
Posted 16 hours ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Contact the job poster

Imran Khan

Recruiter @ Tekfortune Inc.

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Hybrid in Sunnyvale, California

•

19d ago

Firmware Engineer Post-Silicon Validation Location: Sunnyvale, CA Hybrid work 2 to 3 days a week FTE/Fulltime Salary: Market Immediate start Job Summary We are seeking a Firmware Engineer to join the Reality Labs Silicon Validation team. In this role, you will develop, debug, and maintain embedded firmware that enables post-silicon bring-up, validation, and characterization of next-generation silicon platforms. You will work closely with silicon validation, hardware, ASIC, and software tea

Easy Apply

Full-time, Third Party

Depends on Experience

Principal Engineer, Silicon Validation

San Jose, California

•

Today

Principal Engineer, Silicon Validation Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar

Full-time

USD 200,000.00 - 255,000.00 per year

Firmware Engineer Post-Silicon Validation

Hybrid in Sunnyvale, California

•

13d ago

Firmware Engineer Post-Silicon ValidationLocation: Sunnyvale, CAHybrid work 2 to 3 days a weekJob SummaryWe are seeking a Firmware Engineer to join the Reality Labs Silicon Validation team. In this role, you will develop, debug, and maintain embedded firmware that enables post-silicon bring-up, validation, and characterization of next-generation silicon platforms. You will work closely with silicon validation, hardware, ASIC, and software teams to ensure high-quality silicon delivery through eff

Easy Apply

Full-time

$140,000 - $165,000

Hardware & Silicon Validation Principal Engineer

Santa Clara, California

•

Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 150,680.00 - 225,700.00 per year

Job Details

Skills

Automated Testing
Interfaces
Integrated Circuit
I2C
Root Cause Analysis
Verification And Validation

Summary

Role:                 SoC Validation Engineer_ Pre & Post-Silicon
Location:         Sunnyvale CA (Onsite)
 
 
Summary 

We are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems   including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs   with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production. 
 
 
Key Responsibilities 
 Pre-Silicon Validation

Develop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers), Reset Architecture, Ethernet MAC/PHY, and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)

Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level

Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior

Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces

Perform functional coverage analysis and drive coverage closure across IP blocks

Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews

Execute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integration

Post-Silicon Validation

Bring up and validate SoC IPs on first silicon and platform boards

Develop and execute post-silicon test plans covering:

Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions

Reset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection

Ethernet: Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping

I/O: Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing

Debug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx, and embedded trace tools

Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams

Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions

Develop and maintain automated test frameworks for regression and production testing

Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug

General

Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases

Develop Python/Perl/Tcl scripts for test automation, log parsing, and result analysis

Participate in silicon bring-up triage, failure analysis, and bug review meetings

Mentor junior engineers and drive process improvements in validation methodology

Interface with IP vendors for third-party IP integration, compliance, and issue resolution

 
Required Qualifications

Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field

Experience: 4 10+ years in SoC validation (pre-silicon and/or post-silicon)

Deep understanding of SoC architecture and IP integration concepts

Dice Id: 90941404
Position Id: LAKSJDppp
Posted 16 hours ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Contact the job poster

Imran Khan

Recruiter @ Tekfortune Inc.

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Hybrid in Sunnyvale, California

•

19d ago

Easy Apply

Full-time, Third Party

Depends on Experience

Principal Engineer, Silicon Validation

San Jose, California

•

Today

Full-time

USD 200,000.00 - 255,000.00 per year

Firmware Engineer Post-Silicon Validation

Hybrid in Sunnyvale, California

•

13d ago

Easy Apply

Full-time

$140,000 - $165,000

Hardware & Silicon Validation Principal Engineer

Santa Clara, California

•

Today

Full-time

USD 150,680.00 - 225,700.00 per year

SoC Validation Engineer_ Pre & Post-Silicon

Skills

Summary

Dice Job Match Score™

Imran Khan

Similar Jobs

SoC Validation Engineer_ Pre & Post-Silicon

Job Details

Skills

Summary

Dice Job Match Score™

Imran Khan

Similar Jobs