JEDEC Jobs in San Jose, CA

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Principal PCB Design Engineer

Commscope

Sunnyvale, California, USA

Full-time

In our 'always on' world, we believe it's essential to have a genuine connection with the work you do. RUCKUS Networks, part of CommScope, specializes in delivering high-performance networking solutions while focusing on creating purpose-driven networks that perform exceptionally well in challenging environments. RUCKUS Networks leverages advanced technologies like Artificial Intelligence (AI) and Machine Learning (ML) to enhance network performance and reduce total cost of ownership. How You'll

Sr. Signal Integrity and Power Integrity Engineer

AMD (Advanced Micro Devices)

Santa Clara, California, USA

Full-time

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellenc

SoC Architect, Memory Subsystem (Principal Engineer)

Samsung Electronics America

San Jose, California, USA

Full-time

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Principal Engineer - Silicon Validation Engineer

Marvell Semiconductor Inc.

Santa Clara, California, USA

Full-time

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

Senior Reliability Engineer

NVIDIA Corporation

Santa Clara, California, USA

Full-time

For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of innovative visual computing - the field has expanded to encompass personal computer games, movie production, product design, artificial intelligence, medical diagnosis and scientific research. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. NV

PCB Layout designer

Ace Technologies, Inc.

Mountain View, California, USA

Third Party, Contract

Mt. View, CAClient is open to contract to hireMinimum 5 plus years, more experienced the better, onsite 3 days a weekLooking for 2 contractors (will want to convert)1 in Mtn View, CA 1 in bostonHybrid- 3 days onsite pick your own daysPCB layout of high-speed, high-density multi-layer printed circuit boards, 14-layers and upCreate a constraint-driven routing methodologyDevelop and maintain a corporate library of component footprintsInterface to outside PCB layout service bureaus when necessaryWor

DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.

California, USA

Full-time, Third Party, Contract

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f