rtl design Jobs

241 - 260 of 260 Jobs

Design Verification EngineerJob Title - Design Verification Engineer

Xoriant CorporationCompany Name - Xoriant Corporation

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Austin, Texas, USA

Contract

Job Title: Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project) Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite) Description As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updatesDebug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean re

Senior Synthesis Flow CAD EngineerJob Title - Senior Synthesis Flow CAD Engineer

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Santa Clara, California, USA

Full-time

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify huma

Clock Distribution Engineer, DojoJob Title - Clock Distribution Engineer, Dojo

Tesla MotorsCompany Name - Tesla Motors

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Palo Alto, California, USA

Full-time

The Dojo Hardware team is looking for a Clock Distribution Engineer to work in Palo Alto, CA. This Engineer will be responsible for the design and implementation of clocks at both the SOC and IP level. Responsibilities Design custom clock distribution from PLL to sub-blocks meeting low latency and jitter specs for various SOC clocks Write modular clock RTL to handle changes, integrating it into designStrong tcl knowledge to automate the clock tree generation based on bottoms-up load feedbackWor

STAEngineerJob Title - STAEngineer

CloudiousCompany Name - Cloudious

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San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficien

Senior ASIC Timing EngineerJob Title - Senior ASIC Timing Engineer

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Westford, Massachusetts, USA

Full-time

Senior ASIC Verification Engineer - HSIOJob Title - Senior ASIC Verification Engineer - HSIO

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Westford, Massachusetts, USA

Full-time

NVIDIA is seeking a highly motivated Senior Design Verification Engineer to play a critical role in verifying next-generation NVLink High-Speed I/O (HSIO) controllers for industry-leading GPUs. This is a unique opportunity to contribute to cutting-edge products spanning consumer graphics, self-driving vehicles, and artificial intelligence-all within a collaborative, technology-driven environment. At NVIDIA, we're redefining the future of computing. From revolutionizing gaming and cinematic visua

Senior ASIC Front End Infrastructure EngineerJob Title - Senior ASIC Front End Infrastructure Engineer

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Remote or Santa Clara, California, USA

Full-time

NVIDIA is seeking elite ASIC RTL/Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to artificial intelligence to self-driving cars and supercomputers. Our team of dedicated Infrastructure engineers continuously upgrades the NVIDIA Hardware design environment. We focus relentlessly

Senior GPU Low Power ArchitectJob Title - Senior GPU Low Power Architect

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Santa Clara, California, USA

Full-time

We are looking for a Senior GPU Low Power Architect within our Hardware Team! NVIDIA is known as a world leader in providing energy-efficient high-performance products, and we continue to invest in the research and development of hyper-efficient GPU and SOC architectures that power AI, Automotive, Graphics, and Mobile products. Widely considered to be one of the technology world's most desirable employers, you will interact with world class engineers on the cutting edge of emerging GPU and AI te

Senior ASIC Design Engineer- Emulation (HAPS Engineer)Job Title - Senior ASIC Design Engineer- Emulation (HAPS Engineer)

CloudiousCompany Name - Cloudious

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San Jose, California, USA

Contract

Position: Senior ASIC Design Engineer- Emulation (HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top

Hardware Security, Lead EngineerJob Title - Hardware Security, Lead Engineer

Oracle CorporationCompany Name - Oracle Corporation

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Santa Clara, California, USA

Full-time

Job Description Department Description As part of the Oracle Hardware Development (OHD) Hardware Engineering Organization, you will be involved in developing the next generation of Oracle hardware that underlies all of Oracle's Cloud and Enterprise platform offerings. These systems utilize leading edge technology to deliver record-breaking performance, simplified management, security, self-monitoring and diagnosis as well as cost-saving efficiencies. You will apply your expertise in detailed s

Design verification EngineerJob Title - Design verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

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Mountain View, California, USA

Contract, Third Party

A client of Innova Solutions is immediately hiring a Design verification Engineer Position type: Contract Duration: Contract Location: Mountain View, CA (Hybrid) As a Design verification Engineer, you will need: Must-Have Skills: 9+ years of experience as Design Verification EngineerStrong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-

Emulation EngineerJob Title - Emulation Engineer

eInfochips IncCompany Name - eInfochips Inc

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San Jose, California, USA

Full-time, Third Party

Job Description:What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance obj

Emulation Engineer at San Jose CAJob Title - Emulation Engineer at San Jose CA

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Job Description: Develop state-of-the-art emulation environments that will be used to evaluate the performance and functionality of multi-terabit systems.Developing emulation infrastructure using C/C++ and TCLAs a team member, work closely with the design, DV, power, and post-silicon diagnostic teams.Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process.Develop tests to generate complex traffic, and performance scenarios to catch potential post

FPGA EngineerJob Title - FPGA Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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Sunnyvale, California, USA

Contract

A globally leading technology company is looking for an experienced FPGA Engineer to architect, design, and validate RTL for advanced display subsystem prototypes. In this role, you will collaborate with cross-functional teams, contribute to hardware bring-up, and support low-level software integration. Strong skills in digital interface debugging, FPGA tools, and C/C++ firmware development are essential. If you're passionate about innovation and display technology, we invite you to apply! Job

DV Engineers DDR (either IP or SoC level experience)- RemoteJob Title - DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.Company Name - E-Solutions, Inc.

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California, USA

Full-time, Contract, Third Party

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

FPGA Engineer IVJob Title - FPGA Engineer IV

Ascendion Inc.Company Name - Ascendion Inc.

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Redmond, Washington, USA

Full-time

About Ascendion Ascendion is a full-service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 11,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to e

Silicon DD Engineer IVJob Title - Silicon DD Engineer IV

BCforwardCompany Name - BCforward

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Kirkland, Washington, USA

Contract

Silicon DD Engineer IV BCforward is currently seeking a highly motivated Silicon DD Engineer IV for an Onsite opportunity. Position Title: Silicon DD Engineer IV Location: Kirkland, WA Anticipated Start Date: 8/01/2025 Please note this is the target date and it is subject to change. BCforward will send official notice ahead of a confirmed start date. Expected Duration: 12 Months (Potential for Extension) Job Type: Contract - [FULL TIME (40 Hours a week)] Pay Range: $95.73/hr-$100.48/hr Pl

Silicon DV Engineer IIIJob Title - Silicon DV Engineer III

BCforwardCompany Name - BCforward

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California, USA

Contract

Silicon DV Engineer BCforward is currently seeking a highly motivated Silicon DV Engineer for a Remote opportunity Position Title: Silicon DV Engineer Location: Remote Anticipated Start Date: 8/11/2025 Please note this is the target date and is subject to change. BCforward will send official notice ahead of a confirmed start date. Expected Duration: 6+ Months Job Type: Contract - [FULL TIME (40 Hours a week)] Pay Range: $85/hr-$95/hr Please note that actual compensation may vary within

Design Verification EngineerJob Title - Design Verification Engineer

JConnect IncCompany Name - JConnect Inc

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San Jose, California, USA

Full-time

Role: Design Verification Engineers (SoC-5, PCIe-5)Location: Bay AreaSalary: 160-240k (DOE) Free health insurancePTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from speci