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ASIC
SystemVerilog
UVM

Summary

Job Title: Senior ASIC Design Verification Engineer

Location: Austin, TX / San Francisco, CA (Onsite/Hybrid)

Job Summary

We are seeking an experienced Senior ASIC Design Verification Engineer to verify next-generation CPU, AI/ML, and SoC designs. The ideal candidate will have strong expertise in developing UVM-based verification environments, functional coverage, RTL debug, and constrained-random verification while working closely with design and architecture teams from specification through tape-out.

Primary Skills (Must Have)

SystemVerilog & UVM
Constrained Random Verification (CRV)
Functional Coverage & Coverage Closure
RTL Debug & ASIC/SoC Verification

Key Responsibilities

Develop UVM/SystemVerilog verification environments.
Create test plans, testbenches, sequences, scoreboards, and checkers.
Perform block-level and full-chip ASIC/SoC verification.
Execute constrained-random and directed testing.
Debug RTL issues and drive functional coverage closure.
Collaborate with design, architecture, and validation teams.
Support regression, verification signoff, and tape-out activities.

Preferred Skills

CPU/Processor or Memory Subsystem Verification
SVA (SystemVerilog Assertions)
ARM, RISC, AI/ML Accelerator, or GPU verification
Experience with VCS, Questa, or Xcelium
Python or C/C++

Education

Bachelor''''''''s or Master''''''''s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Thanks,

Vinutha

Venturesoft.ai

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10119168
Position Id: 9038917
Posted 1 day ago

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Vinutha Jagadeesh

VentureSoft Global Recruiter @ VentureSoft Global

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ASIC Design Verification Engineer

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Vinutha Jagadeesh

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