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Description
APPLE INC has the following available in Austin, Texas. Generation of Block and Chip-Level Specifications: Defining and documenting functional and performance requirements for blocks and chips, ensuring they align with system-level goals for high-speed, low-power communication. Transistor-Level Circuit Design: Designing complex analog and mixed-signal circuits at the transistor level, ensuring precision in meeting power, performance, and area constraints; Being familiar with 'Virtuoso' to test the design with various options & environment. Block-Level Verification: Conducting block-level simulations and analyses to ensure that circuits meet performance, power, and area requirements, verifying each design's functionality. Clock Distribution and CDR Circuit Design: Designing clock distribution circuits to ensure high-speed clocks are effectively delivered to various chip components; Focusing on designing CDR circuits that recover data with minimal error; Using SERDES system to determine circuits required in the task. Investigation of Power-Efficient Clocking Architectures: Investigating new clocking architectures to reduce power consumption in the semiconductor. This includes examining novel approaches to clocking that minimize the power draw of the chip's clocking circuits, which typically account for a significant portion of total power consumption. Duty Cycle Corrector and Phase Interpolator Design: Designing and optimizing Duty Cycle Correctors (DCC) and Phase Interpolators (PI) to improve clock quality. Designing precise comparators and samplers for the DCC, focusing on layout optimization. Focusing on improving the linearity and step size of the Phase Interpolator within the CDR block to enhance its performance and reduce power consumption. 100MHz Reference Clock Receiver: Designing the clock receiver to deliver a 100 MHz clock from the pad to the PLL with minimal jitter contribution Designing a 50-ohm termination to avoid reflections from the chip Redesigning the clock receiver to prevent degradation due to headroom issues caused by the reduction in power supply voltage from 1.2V to 1.06V Environment Testing and Reliability Analysis: Testing the chips under various process, temperature, and voltage conditions to ensure their robustness and functionality in diverse environments. 40 hours/week.
Minimum Qualifications
Master's Degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.
Education and/or experience must include:
Designing and analyzing high-speed analog and mixed-signal building blocks including PLL, LDO, ADC, DAC and Phase-Interpolator.
Leveraging end-to-end SERDES systems including TX/RX design and channel characteristics and equalization techniques.
Utilizing RTL/Verilog modeling to develop models for mixed-signal blocks to help with system level design verification.
Modeling MATLAB for performance analysis of SERDES (jitter tolerance, equalization analysis).
Leveraging testing equipment including spectrum analyzers, oscilloscope, and signal generators for post-silicon validation and testing.
Utilizing layout techniques for analog and high-speed circuits including matching, noise to ensure the post-layout performance.
Leveraging signal processing for design and analysis including filtering, equalization, and spectral analysis.
Using Python and Shell scripting to automate design simulations and for data analysis.
Utilizing design validation tools including EMIR, static timing analysis, and DFT to ensure design robustness and manufacturability.
Preferred Qualifications
N/A
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 90733111
- Position Id: 3dbcca6db39b8b24c36d7a0cd36d0581
- Posted 6 days ago
