Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role and ResponsibilitiesAs a Staff Timing (STA) Engineer, you will join the GPU Physical Design team to work on ensuring timing integrity and signoff readiness for Samsung's next-generation GPU IPs used in premium smartphones and adjacent market segments.
In this mid-level individual contributor role, you will collaborate closely with RTL, physical design, SoC integration, and EDA partners to develop and implement timing analysis and convergent strategies for complex GPU designs. You bring curiosity, hands-on STA expertise, a solid understanding of ASIC design flows, and a collaborative mindset to apply sound methodology and deliver high-quality timing closure and power recovery across functional and test modes.
- You execute hands-on timing analysis at top level, understand timing margin, generate and debug timing constraints for complex, multi-clock GPU IPs across functional and test scenarios. Contribute to improvement in model extraction, timing convergence, correlation, timing robustness, and power recovery.
- support cross-functional collaboration with RTL, physical design, and SoC teams to identify, debug, and resolve timing issues impacting block-level and full-chip closure, ensuring alignment between logical intent and physical implementation
- You Identify tool bugs and inefficiencies, influence flow and methodology enhancement, leverage industry-standard tools and exploring best practices-including OCV mitigation, low-power techniques, and ML-assisted exploration-to improve timing quality, convergence, and predictability.
- You support timing closure and signoff readiness by analyzing timing paths, providing feedback to floorplan, clocking and physical design, and applying timing budgeting, derating, and multi-voltage methodologies across advanced process nodes.
- You take initiative on moderate-to-complex projects, communicating openly and clearly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging GPU technologies
Skills and Qualifications- 6+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 4+ years of experience with a Master's Degree, or 2+ years of experience with a Ph.D.
- Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
- Working knowledge and experience with POCV, derating methodologies, and timing analysis.
- Strong hands-on experience with industry-standard STA tools (e.g., PrimeTime, Tempus).
- Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
- Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
- Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
- Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
- Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
- Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment.
Nice to have:
- Familiarity with advanced FinFET process nodes (5nm or smaller).
- Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools.
- Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure.
Our Team The Advanced Design Technology and Design Implementation teams play a critical role in enabling GPU and system-level development within Samsung SARC/ACL and the broader System LSI organization. Operating at the intersection of design technology and physical implementation, we partner closely with Foundry from early technology exploration through the full development cycle. Spanning advanced design methodologies, GPU physical design, CAD, and DTCO, we accelerate adoption of leading technology nodes and deliver optimized power, performance, area (PPA), silicon quality, and turnaround time for next-generation IP solutions.
You will join a highly collaborative, fast-paced environment working across parallel development cycles with direct impact on consumer technologies used worldwide. Here, you'll help build what's next: experimenting with new ideas, broadening your technical expertise, and solving impactful challenges alongside talented teammates who value ownership, continuous learning, and growth.
Total Rewards
At Samsung - SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $226,600. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.
Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
Additionally, this role might be eligible to participate in long term incentive plan and relocation.
This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).
Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
U.S. Export Control
This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.
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