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Formal Verification Engineer - #26-21752

U.S. Tech Solutions Inc.

Ben Lomond, California • Today

Easy Apply

Contract

$80 - $85

Job Details

Skills

VERIFICATION
UVM
VERILOG
SYSTEMVERILOG

Summary

Duration: 12+ Months

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

5-7 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
Strong background in C/C++ development in a Linux Environment.
Strong debug skills and experience with debug tools such as Gdb, Valgrind.
Proficient in Object Oriented programming, STL, computer architecture and data structures.
Knowledge of Perl and Makefiles.
Experience in Verilog/SystemVerilog/SystemC, preferred.
Experience in C/Verilog environment using DPI/PLI, preferred.
Strong analytical skills and attention to detail.
Excellent written and communication skills.

About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

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Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: usts
Position Id: 26-21752
Posted 3 hours ago

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Job Details

Skills

VERIFICATION
UVM
VERILOG
SYSTEMVERILOG

Summary

Duration: 12+ Months

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

5-7 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
Strong background in C/C++ development in a Linux Environment.
Strong debug skills and experience with debug tools such as Gdb, Valgrind.
Proficient in Object Oriented programming, STL, computer architecture and data structures.
Knowledge of Perl and Makefiles.
Experience in Verilog/SystemVerilog/SystemC, preferred.
Experience in C/Verilog environment using DPI/PLI, preferred.
Strong analytical skills and attention to detail.
Excellent written and communication skills.

Dice Id: usts
Position Id: 26-21752
Posted 3 hours ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Create job alert

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