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Description
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Define the Micro-architecture of the CPU hardware. Develop the CPU hardware using a Hardware-Description-Language. Perform functional debug and closure of the design. Responsible for timing and power closure of the design for the target Frequency and Power. Prepare documentation of the Design Specification. Design and develop hardware for Apple's mobile devices. Evaluate new ideas and features for the Central Processing Unit (CPU) hardware. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,294 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.
PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: ;br>
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Minimum Qualifications
Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
Experience and/or education must include:
Knowledge of Microprocessor architecture, including instruction fetch and decode, instruction scheduling and register renaming, out-of-order execution, integer and floating-point execution, load/store execution (or cache), and memory subsystems.
Utilizing System Verilog or Verilog to write RTL for Machine learning unit within the CPU.
Utilizing Scripting languages including Python or Perl to develop automation scripts for RTL design.
Experience in Computer Architecture to optimize performance and power of CPUs.
Utilizing Logic design knowledge to explore and implement advanced compression techniques in CPUs.
Using Synopsys Verdi or Cadence Indago to analyze simulation waveforms.
Writing RTL assertions and providing guidance to generate stimulus, analyze design, meet coverage targets and fix failures.
Working on Physical design aspects to ensure the design meets specific timing goals.
Deploying low-power design techniques like clock gating, power gating, and DVFM to optimize power.
Utilizing CDC, RDC tools/techniques, and knowledge of multiple clock domains and multiple reset domains.
Utilizing design knowledge with the silicon validation and bring-up to accelerate the debug process and ensure robust product qualification through early identification and resolution.
Preferred Qualifications
N/A
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 90733111
- Position Id: 2ea42a0de12d595fc3f4d41b0a3ff708
- Posted 5 days ago
