Job Title: FPGA Design Engineer
DOD (Dept of Defense) / Department of War (DOW) projects
ship required due to program access requirements.
Must be eligible to obtain DOD Clearance
Duration: up to 4 months Contract with possible extensions
Location: Remote work (Work from home)
Work Schedule: 4/10 First Shift, Monday to Thursday 10 hours per day.
Pay Rate: $80/hr on W2 [the pay rate may differ depending on your skills, education, experience, and other qualifications]
Featured Benefits:
· Medical Insurance in compliance with the ACA
· 401(k)
· Sick leave in compliance with applicable state, federal, and local laws
Job Description:
· Write Verilog code to implement the logic (e.g., data processing pipelines for ADP/DDP, serial comms for HSPCI).
· Create Firmware Requirements Specifications (FRS) and Firmware Design Descriptions (FDD); these are formal deliverables tied to program milestones.
· Simulate the designs to verify they behave correctly before hardware is ready.
Integration & Test
· Load the FPGA code onto prototype hardware (ADP boards are already built; DDP/HSPCI are in development).
· Support integration teams by fixing problems (PTRs) and refining the design as needed.
Required Skills:
· Verilog
· FPGA Design Toolchain (Vivado/Quartus)
· RTL Coding & Simulation
· Documentation (FRS/FDD)
· Version Control (Git)
