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VGAI Solutions Inc

Hybrid in Austin, Texas • Yesterday

Easy Apply

Contract

55 - 60

Analog IC Design Engineer

Kforce Technology Staffing

Austin, Texas • Yesterday

Full-time

$120,000 - $150,000 annually

Senior or Principal Analog IC Design Engineer

Kforce Technology Staffing

Austin, Texas • Yesterday

Full-time

$155,000 - $190,000 annually

Senior Serdes System Design Engineer/Architect

Broadcom Corporation

Austin, Texas • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Analog Layout Automation Engineer

Apple, Inc.

Austin, Texas • Today

Full-time

Principal Analog Validation Engineer

NXP Semiconductors N.V.

Austin, Texas • Today

Full-time

Job Details

Skills

Amazon S3
Analytical Skill
Collaboration
Communication
Computer Engineering
Conflict Resolution
Engineering Support
Intellectual Property
Root Cause Analysis
Semiconductors
Signal Integrity
Problem Solving
Regulatory Compliance
SERDES
Distribution
Electrical Engineering
FOCUS
IP
Screening
System On A Chip
Testing
Debugging

Summary

SERDES PHY Integration & Validation Engineer

Location: Austin, TX
Experience: 9+ years preferred
Education: Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Role Overview

AMD’s 3rd Party IP Team is seeking an experienced engineer with a strong background in SERDES PHYs or Memory PHYs to support the integration of third-party PHY IP across AMD products.

The role involves both pre-silicon IP integration and post-silicon validation and support, with a focus on electrical analysis, signal integrity, power integrity, clock integrity, and functional performance across different SoC platforms.

The ideal candidate will have a solid understanding of PHY architecture and electrical characteristics, along with experience supporting silicon validation, characterization, compliance testing, or electrical testing.

Key Responsibilities

Support pre-silicon integration of third-party SERDES PHY IP across various AMD products and SoC platforms.
Provide post-silicon engineering support for SERDES PHY IP across different validation and testing scenarios.
Perform and support electrical analysis related to power integrity, signal integrity, and clock integrity.
Help ensure reliable SERDES PHY operation across multiple SoC environments.
Collaborate with post-silicon engineering teams on production screening, silicon characterization, compliance testing, and functional validation.
Troubleshoot PHY-related electrical and functional issues and support root-cause analysis.
Work closely with cross-functional engineering teams to resolve integration and validation challenges.

Required / Core Technical Skills

Strong technical background in SERDES PHYs or Memory PHYs.
Understanding of PHY IP integration and semiconductor SoC environments.
Knowledge of electrical characteristics affecting PHY performance, including power, signal, and clock integrity.
Strong analytical, debugging, and problem-solving skills.
Ability to collaborate effectively with cross-functional engineering teams.
Excellent written and verbal communication skills.

Preferred Technical Experience

SERDES PHY or Memory PHY design experience.
Understanding of power noise generation and noise sensitivity.
Fundamentals of signal integrity, including:
- Termination impedance
- Characteristic impedance
- Transmission lines
Knowledge of clock distribution and clock specifications, including jitter and duty-cycle distortion (DCD).
Hands-on laboratory experience with SERDES PHY functional validation, electrical testing, or compliance testing.
Experience with post-silicon characterization, production screening, and functional validation.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91027520
Position Id: 9121803
Posted 1 day ago

Fitment

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Contact the job poster

Sudhir Dubey

Recruiter @ VGAI Solutions Inc

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Job Details

Skills

Amazon S3
Analytical Skill
Collaboration
Communication
Computer Engineering
Conflict Resolution
Engineering Support
Intellectual Property
Root Cause Analysis
Semiconductors
Signal Integrity
Problem Solving
Regulatory Compliance
SERDES
Distribution
Electrical Engineering
FOCUS
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Screening
System On A Chip
Testing
Debugging

Summary

SERDES PHY Integration & Validation Engineer

Location: Austin, TX
Experience: 9+ years preferred
Education: Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Role Overview

AMD’s 3rd Party IP Team is seeking an experienced engineer with a strong background in SERDES PHYs or Memory PHYs to support the integration of third-party PHY IP across AMD products.

Key Responsibilities

Support pre-silicon integration of third-party SERDES PHY IP across various AMD products and SoC platforms.
Provide post-silicon engineering support for SERDES PHY IP across different validation and testing scenarios.
Perform and support electrical analysis related to power integrity, signal integrity, and clock integrity.
Help ensure reliable SERDES PHY operation across multiple SoC environments.
Collaborate with post-silicon engineering teams on production screening, silicon characterization, compliance testing, and functional validation.
Troubleshoot PHY-related electrical and functional issues and support root-cause analysis.
Work closely with cross-functional engineering teams to resolve integration and validation challenges.

Required / Core Technical Skills

Strong technical background in SERDES PHYs or Memory PHYs.
Understanding of PHY IP integration and semiconductor SoC environments.
Knowledge of electrical characteristics affecting PHY performance, including power, signal, and clock integrity.
Strong analytical, debugging, and problem-solving skills.
Ability to collaborate effectively with cross-functional engineering teams.
Excellent written and verbal communication skills.

Preferred Technical Experience

SERDES PHY or Memory PHY design experience.
Understanding of power noise generation and noise sensitivity.
Fundamentals of signal integrity, including:
- Termination impedance
- Characteristic impedance
- Transmission lines
Knowledge of clock distribution and clock specifications, including jitter and duty-cycle distortion (DCD).
Hands-on laboratory experience with SERDES PHY functional validation, electrical testing, or compliance testing.
Experience with post-silicon characterization, production screening, and functional validation.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.

Dice Id: 91027520
Position Id: 9121803
Posted 1 day ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Contact the job poster

Sudhir Dubey

Recruiter @ VGAI Solutions Inc

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

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Analog Designer - SERDES

Skills

Summary

SERDES PHY Integration & Validation Engineer

Role Overview

Key Responsibilities

Required / Core Technical Skills

Preferred Technical Experience

Education Requirements

Dice Job Match Score™

Sudhir Dubey

Similar Jobs

Analog Designer - SERDES

Job Details

Skills

Summary

SERDES PHY Integration & Validation Engineer

Role Overview

Key Responsibilities

Required / Core Technical Skills

Preferred Technical Experience

Education Requirements

Dice Job Match Score™

Sudhir Dubey

Similar Jobs