SERDES PHY Integration & Validation Engineer

Location: Austin, TX
Experience: 9+ years preferred
Education: Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Role Overview

AMD’s 3rd Party IP Team is seeking an experienced engineer with a strong background in SERDES PHYs or Memory PHYs to support the integration of third-party PHY IP across AMD products.

The role involves both pre-silicon IP integration and post-silicon validation and support, with a focus on electrical analysis, signal integrity, power integrity, clock integrity, and functional performance across different SoC platforms.

The ideal candidate will have a solid understanding of PHY architecture and electrical characteristics, along with experience supporting silicon validation, characterization, compliance testing, or electrical testing.

Key Responsibilities

• Support pre-silicon integration of third-party SERDES PHY IP across various AMD products and SoC platforms.

• Provide post-silicon engineering support for SERDES PHY IP across different validation and testing scenarios.

• Perform and support electrical analysis related to power integrity, signal integrity, and clock integrity.

• Help ensure reliable SERDES PHY operation across multiple SoC environments.

• Collaborate with post-silicon engineering teams on production screening, silicon characterization, compliance testing, and functional validation.

• Troubleshoot PHY-related electrical and functional issues and support root-cause analysis.

• Work closely with cross-functional engineering teams to resolve integration and validation challenges.

Required / Core Technical Skills

• Strong technical background in SERDES PHYs or Memory PHYs.

• Understanding of PHY IP integration and semiconductor SoC environments.

• Knowledge of electrical characteristics affecting PHY performance, including power, signal, and clock integrity.

• Strong analytical, debugging, and problem-solving skills.

• Ability to collaborate effectively with cross-functional engineering teams.

• Excellent written and verbal communication skills.

Preferred Technical Experience

• SERDES PHY or Memory PHY design experience.

• Understanding of power noise generation and noise sensitivity.

• Fundamentals of signal integrity, including:

  • Termination impedance

  • Characteristic impedance

  • Transmission lines

• Knowledge of clock distribution and clock specifications, including jitter and duty-cycle distortion (DCD).

• Hands-on laboratory experience with SERDES PHY functional validation, electrical testing, or compliance testing.

• Experience with post-silicon characterization, production screening, and functional validation.

Education Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.