Verification and Validation (V&V) Engineer W/ Medical OR HealthCare Domain

Job: Design Verification Engineer Location: Sunnyvale, CA 94085 (On-site) Duration: Fulltime Job Description Primary Skills:Verilog, System Verilog, C/C++ based verification, and UVM methodology Description: Job Description: We are seeking a talented and experienced Design Verification Engineer to join our dynamic team. The ideal candidate will have a strong background in universal verification methodologies and hands-on experience in verifying complex digital designs. Responsibilities: Defin