New York, New York
•
22d ago
About the Position We are looking to hire an ASIC Physical Design Engineer, who is also experienced reading and writing RTL, to help us design, test and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to l
Full-time
