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PD Engineer

Della Infotech

Remote • Today

Easy Apply

Contract

$55 - $70

PD Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 107,400.00 - 161,200.00 per year

PD Engineer

Carman Solutions Group

Sunnyvale, California • Today

Easy Apply

Full-time

Depends on Experience

PD Engineer

Sivaltech

San Diego, California • 13d ago

Easy Apply

Full-time, Third Party

180,000 - 200,000

EPS/PD Principal Asset Engineer

Covestro

Baytown, Texas • Today

Full-time

ASIC Implementation Engineer PD

Broadcom Corporation

San Jose, California • Today

Full-time

USD 121,900.00 - 195,000.00 per year

Health Sensing PD - Mechanical Engineer

Apple, Inc.

San Francisco, California • Today

Full-time

Optical Sensing PD - Mechanical Engineer

Apple, Inc.

San Francisco, California • Today

Full-time

Physical Design Engineer (PD/PnR)

K-Tek Resourcing LLC

Austin, Texas • 25d ago

Easy Apply

Full-time

130,000 - 140,000

Color Resin Engineer - Materials PD

Apple, Inc.

Cupertino, California • Today

Full-time

Oracle cloud consultant with AI experience (Must have: Oracle Cloud Infrastructure / OCI AI/ML - AI/ML Services, Oracle PLM / Oracle Cloud PD and PDH modules, AI/ML Solution Design & Deployment)

Accion Labs

Hybrid in Pittsburgh, Pennsylvania • Today

Easy Apply

Contract

Depends on Experience

Physical Design Engineer & DV Engineers

K-Tek Resourcing LLC

Sunnyvale, California • 15d ago

Easy Apply

Full-time

160,000 - 170,000

Audio PD Engineer

Apple, Inc.

Cupertino, California • Today

Full-time

Space Systems Lead Engineer (Product Development)

Advanced Cooling Technologies, Inc

Anaheim, California • Today

Full-time

Space Systems Lead Engineer (Product Development)

Advanced Cooling Technologies, Inc

Lancaster, Pennsylvania • Today

Full-time

System Engineer | INT PD

Texas Instruments Incorporated

Dallas, Texas • Today

Full-time

ASIC Physical Design Engineer

Jane Street

New York, New York • 5d ago

Full-time

Salesforce Developer with Agent force

Comprehensive Resources Inc.

Dallas, Texas • Today

Easy Apply

Full-time, Part-time, Third Party, Contract

Engineer, Packaging

HIKMA PHARMACEUTICAL

Columbus, Ohio • Today

Full-time

Process Engineer

First Quality Enterprises, Inc.

Macon, Georgia • Today

Full-time

Process Engineer

Danone

Louisville, Colorado • Today

Full-time

USD 82,000.00 - 118,000.00 per year

Principal AI Forward Deployment Engineer

Cadence Design Systems Inc

Oregon • Today

Full-time

Process Engineer I

First Quality Enterprises, Inc.

McElhattan, Pennsylvania • Today

Full-time

Field Engineer - Elevator & Escalator

Metropolitan Transportation Authority

New York, New York • Today

Full-time

USD 50.34 per hour

Product Development Engineer

Amcor Inc

Remote or Michigan • Today

Full-time

USD 50,000.00 per year

Process Engineer

First Quality Enterprises, Inc.

Lewistown, Pennsylvania • Today

Full-time

Product Engineer Electrical

XA.net

Avon Lake, Ohio • Today

Full-time

iPhone Product Design Engineering Program Manager (PD EPM)

Apple, Inc.

Cupertino, California • Today

Full-time

Engineer II, Packaging

HIKMA PHARMACEUTICAL

Columbus, Ohio • Today

Full-time

Product Development Engineer, Product Operations

AMD (Advanced Micro Devices)

Secaucus, New Jersey • Today

Full-time

USD 96,600.00 per year

Job Details

Skills

Cadence
ASIC
System On A Chip
Tcl
RTL

Summary

Job Responsibilities:

Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.

Preferred Qualifications:

7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10511336
Position Id: 9059956
Posted 15 hours ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Contact the job poster

Andrew Fugle

Della Infotech Recruiter @ Della Infotech

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Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

Lead ASIC DFT Engineer

Remote

•

Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Asics Engineer

Remote

•

Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Lead ASIC DFT Engineer

Remote

•

15d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Contract, Third Party

110 - 120

Job Details

Skills

Cadence
ASIC
System On A Chip
Tcl
RTL

Summary

Job Responsibilities:

Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.

Preferred Qualifications:

7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Dice Id: 10511336
Position Id: 9059956
Posted 15 hours ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Contact the job poster

Andrew Fugle

Della Infotech Recruiter @ Della Infotech

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

•

Today

Full-time

USD 191,146.00 - 212,053.00 per year

Lead ASIC DFT Engineer

Remote

•

Today

Full-time

Asics Engineer

Remote

•

Today

Full-time

Lead ASIC DFT Engineer

Remote

•

15d ago

Easy Apply

Contract, Third Party

110 - 120