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PCIe Verification Engineer

TekLeaders, Inc

Remote or San Francisco, California • Today

Easy Apply

Full-time, Part-time, Contract, Third Party

ASIC Verification Engineer

Oxford Global Resources

Hybrid in Burlingame, California • Today

Easy Apply

Contract

$80 - $90

Signal Integrity Engineer

hyve solutions

Fremont, California • Today

Full-time

USD 99,000.00 - 130,000.00 per year

Senior ASIC Emulation Engineer

K2 Space

Remote • Today

Full-time

USD 170,000.00 - 250,000.00 per year

Job Details

Skills

Simulator
C++

Summary

Job Title : PCIe Verification Engineer

Job Location - Address : San Francisco, California, United States - remote

Client Interview : No

Study Level : Bachelor's Degree

Skill Cluster : 423 - DA-Platfrm Pega AccelQ.

Primary Skill : Simulator, C++

Experience : 12+ years

Job Description :

PCIe Protocol IP Verification Expert: Consulting & Turnkey projects Virtusa Semiconductor BU is looking for seasoned professionals in the ASIC Verification domain.
Virtusa is invested in AI/HPC [High Performance Computing] customers who are emphasizing on shift left pre-silicon approaches.
IP integration and interoperability with multiple Vendor PHY is becoming important to be validated for SOC Integration & Bring Up.
Complex System Level Environment targeting latest protocol interfaces & switches for scale up and scale out data centers Virtusa is looking for PCIe protocol experts to integrate the 3rd Party IP s [Synopsys, Cadence, Qualitas & other Vendors] with Rambus PCIe Gen6 controller/PHY & validate with complete regression suite.

Job Description

Application or Product Engineering background with minimum 5 to 10 years of experience is required in SOC/IP Verification.
Deep Knowledge of FW/SW/Driver with linkup/enumeration/device ID/interoperability of PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level . Skills Requirements Digital design with system verilog RTL coding at IP/System Integration level.
Experience with one of the simulators like Questa , VCS & Xelium. Ability to put together top level wrapper with PCIe DUT at sub system level with PHY [Root Complex & End Point Device], clocks/reset & glue logic required.
Ability to understand the complex scripted simulation regression environment with UVM & C/C++ testbenches, modify to enhance the test suit and do the functional verification. Knowledge of Python, C/Perl scripting is required.
Expertise in debugging the complex PCIe bring up scenarios like LTSSM state machines for link up & enumeration steps.
Understand the configurations of all Generations of PCIe combinations for debugging the failures.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 90884655
Position Id: OOJ - 8694-7719-1786117972
Posted 14 hours ago

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Senior ASIC Verification Engineer

San Francisco, California

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At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software developmen

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Digital Verification Engineer

South San Francisco, California

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About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers

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PCIe Silicon Validation & Debug Engineer

Sunnyvale, California

•

2d ago

Job Title: PCIe Silicon Validation & Debug Engineer -Location:Sunnyvale CA (Onsite)Job Type: ContractJobDescription:We are seeking a skilled PCIe Engineer to join our Silicon Engineering team. The ideal candidate will have deepexpertisein PCI Express (PCIe) interfaces and protocols, with hands-on experience in test development, analysis, anddebugacross both pre-silicon and post-silicon environments. You will play a critical role in ensuring the functional correctness, performance, and compliance

Easy Apply

Contract

Depends on Experience

IP Integration Engineer

San Francisco, California

•

Today

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Integration Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple's customers every day! Description In this highly

Full-time

Job Details

Skills

Simulator
C++

Summary

Job Title : PCIe Verification Engineer

Job Location - Address : San Francisco, California, United States - remote

Client Interview : No

Study Level : Bachelor's Degree

Skill Cluster : 423 - DA-Platfrm Pega AccelQ.

Primary Skill : Simulator, C++

Experience : 12+ years

Job Description :

PCIe Protocol IP Verification Expert: Consulting & Turnkey projects Virtusa Semiconductor BU is looking for seasoned professionals in the ASIC Verification domain.
Virtusa is invested in AI/HPC [High Performance Computing] customers who are emphasizing on shift left pre-silicon approaches.
IP integration and interoperability with multiple Vendor PHY is becoming important to be validated for SOC Integration & Bring Up.
Complex System Level Environment targeting latest protocol interfaces & switches for scale up and scale out data centers Virtusa is looking for PCIe protocol experts to integrate the 3rd Party IP s [Synopsys, Cadence, Qualitas & other Vendors] with Rambus PCIe Gen6 controller/PHY & validate with complete regression suite.

Job Description

Application or Product Engineering background with minimum 5 to 10 years of experience is required in SOC/IP Verification.
Deep Knowledge of FW/SW/Driver with linkup/enumeration/device ID/interoperability of PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level . Skills Requirements Digital design with system verilog RTL coding at IP/System Integration level.
Experience with one of the simulators like Questa , VCS & Xelium. Ability to put together top level wrapper with PCIe DUT at sub system level with PHY [Root Complex & End Point Device], clocks/reset & glue logic required.
Ability to understand the complex scripted simulation regression environment with UVM & C/C++ testbenches, modify to enhance the test suit and do the functional verification. Knowledge of Python, C/Perl scripting is required.
Expertise in debugging the complex PCIe bring up scenarios like LTSSM state machines for link up & enumeration steps.
Understand the configurations of all Generations of PCIe combinations for debugging the failures.

Dice Id: 90884655
Position Id: OOJ - 8694-7719-1786117972
Posted 14 hours ago

Fitment

Dice Job Match Score™

🧠 Analyzing your skills...

Create job alert

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Similar Jobs

Senior ASIC Verification Engineer

San Francisco, California

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Today

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Digital Verification Engineer

South San Francisco, California

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USD 131,000.00 - 243,000.00 per year

PCIe Silicon Validation & Debug Engineer

Sunnyvale, California

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2d ago

Easy Apply

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IP Integration Engineer

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