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Remote or San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 143,800.00 - 230,000.00 per year

Top Priority Role --- Remote --- Lead ASIC DFT Engineer

San Jose, California

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2d ago

Good Afternoon, My name is Shivam and I am reaching out from Tanisha Systems Inc. If you are looking for new roles, then please look at below job description. If feel comfortable, then please share updated copy of resume. Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Experience: 15+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug ad

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Contract, Third Party

Depends on Experience

ASIC IP Application Engineer

San Jose, California

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13d ago

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a Senior Application Engineer. Job Description: Job Title: Senior Application Engineer Job Type: Contract Job Location: San Jose, CA Work Schedule: On-site Pay Rate: $65 W2 & $75 C2C, Based on experience Description: The CAD team is looking forhighly analytical and detail-oriented Application Engineer, having an understanding on ASIC Design and building blocks used in suc

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Contract

Depends on Experience

ASIC RTL Design Engineer - Onsite

San Jose, California

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24d ago

Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard interfaces, Ethernet, DDR, DMA, PCIE, SATA, internal IPs, digital CMOS processes, SoC design, Chip definition, Architecture development, modeling, micro-architectural specifications, micro-architectural specifications, logic implementation, emulation, debug Description: JOB DUTIES: The work will expose th

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Contract

57 - 62

ASIC Physical Design Engineer

San Jose, California

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2d ago

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Great base pay, bonus, terrific benefits and exceptional 401k! he MissionStaffRight Associates is recruiting to identify a high-caliber ASICPhysical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (So

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Full-time

170000 - 220000

ASIC / SoC RTL Design Engineer

San Jose, California

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Today

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS SoC design using ARM, PCIe, DDR, and Ethernet. Responsibilities: Architecture definition and micro-specs RTL coding, verification, and debug Synthesis, timing closure, and bring-up Requirements: ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,

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Contract

$60 - $62.50 per hour

Product Planning Engineer-ASIC/SoC

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 140,000.00 per year

Staff/Principal Engineer - ASIC Verification

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff ASIC Design Verification Engineer (Technical role) Position Description: This is a position for Staff technical member of Micron's ASIC Verification and Emul

Full-time

USD 145,000.00 - 286,000.00 per year

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

ASIC Verification Engineer

Saratoga, California

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Today

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Full-time

USD 140,000.00 - 200,000.00 per year

ASIC Methodology Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology, and IP, and foundation IP development. About the Role As a member of the DTECH

Full-time

USD 153,200.00 - 229,800.00 per year

Staff Engineer, ASIC Design Verification

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

Senior ASIC DV Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification e

Full-time

USD 141,300.00 - 226,000.00 per year

Senior Staff Firmware Engineer - low-level firmware/software for advanced Compute, Storage, and Custom ASIC platforms.

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 131,010.00 - 196,300.00 per year

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

ASIC Verification Engineer

San Jose, California

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Today

Company Description Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world's most critical infrastructure-from data centers to next generation cloud and AI platforms-by secur

Full-time

Physical Design Engineer

Mountain View, California

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Yesterday

Physical Design Engineer (PD / PnR / PPA / Timing Closure) Location: Mountain View CA (Onsite) Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical veri

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Contract

Depends on Experience

ASIC/RTL Design Engineer

Hybrid in San Jose, California

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23d ago

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micr

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Contract

Depends on Experience

Principal ASIC Engineer

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Play a key role in architecture and development of advanced verification environments for complex SoC components, while ensuring on time, one time best-in-class quality. Work in the field of Semico

Full-time

USD 233,157.00 - 336,000.00 per year

DFT Engineers

Santa Clara, California

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8d ago

Job Title: DFT Engineers Location: Santa Clara, CA Duration: 12 Months Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level vali

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Full-time, Third Party

Depends on Experience

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