Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

Title: Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills & Experience 3+ years of experience working as a DFT Engineer.Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improv

Hello, Good afternoon, I'm Rahul from Floga Technologies. We are a growing IT services organization delivering scalable technology solutions and are expanding our team with qualified talent. We have an immediate opening for a DFT (Design for Test) Engineer with strong hands-on experience to support a long-term engagement with our client. Must collaborate effectively with cross-functional teams to deliver high-quality solutions. Title: DFT (Design for Test) Engineer Location: santa cla

Job Title: DFT Engineer (ATPG & SSN Streaming Scan Network) Location: San Jose, CA Duration: 12 Months contract+ Experience: 10+ years Key Responsibilities: DFT implementation including Scan, ATPG, simulations, and post-silicon diagnosis at block and SoC levels Verify test patterns using gate-level simulations Collaborate with Synthesis, STA, and Physical Design teams to resolve DFT issues Partner with test engineers during silicon bring-up Hands-on experience with Synopsys TetraMAX, VC

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPGfor SoC or ASIC designsStrong understanding of DFT fundamentalsincluding controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Tes