DFT Engineer

Job Title: DFT Engineers Location: Santa Clara, CA Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock ve

Job Title: DFT Engineer Location: Santa Clara, CA Work Arrangement: Onsite Experience: 5+ Years JOB DESCRIPTION We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-

Were Hiring DFT EngineerWere looking for an experienced DFT Engineer with strong hands-on expertise in Siemens Tessent, ATPG, MBIST, Scan, JTAG/IJTAG, and RTL. The ideal candidate will have a strong understanding of DFT methodologies and experience debugging and improving fault coverage.*Design for Test (DFT) Engineer plays a crucial role in ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) can be thoroughly tested for defects, reliability, and performance.*Hands-on experience

Job Title: DFT Engineers (Multiple Positions) Location: Santa Clara, CA Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understandin