San Diego, California
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2d ago
Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debuggingverificationtestbenches, with the ability to integrateVerificationIPs (VIPs) orDesignIPs into theverificationenvironment.Responsibilities:Develop, enhance, and debug System Veri
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Contract, Third Party
180,000 - 200,000














