Design Verification Engineer

Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute regr

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

Team Red Dog is hiring a Senior Hardware Design Verification Engineer for our client, a leading cloud and software provider and world-class innovation client. In this fully remote role, you will drive hardware design verification for next-generation accelerated networking technologies by developing comprehensive verification strategies, executing SystemVerilog/UVM test environments, and validating complex hardware features through coverage-driven methodologies. You'll collaborate closely with ha

Role: ASIC Verification Engineer Duration: Long-term Contract Location: Remote Must-Have: Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals About the Role: You will join a digital hardware team and contribute across the full silicon development lifecycle from preliminary analysis and micro-architecture definition through RTL development, functional verification, ASIC/FPGA/SoC implementation, on-hardware bring-up, and design documentation. Engineers are expected