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Formal Design Verification Engineer

NUBYT, INC.

San Jose, California • Today

Easy Apply

Third Party, Contract

85 - 95

Design Verification Engineer

SIGNin Solutions Inc.

San Jose, California • 4d ago

Easy Apply

Full-time, Third Party

Depends on Experience

Design Verification Engineer

Reveille Technologies

San Jose, California • 4d ago

Easy Apply

Full-time

Depends on Experience

Design Verification Engineer

Enfycon Inc

San Jose, California • 3d ago

Easy Apply

Third Party, Contract

60 - 70

ASIC Design Verification Engineer - W2 Contract

XFORIA Inc

Menlo Park, California • 5d ago

Easy Apply

Contract

Depends on Experience

GPU Formal Verification Engineer

Apple, Inc.

Santa Clara, California • Today

Full-time

CPU Formal Verification Engineer

Qualcomm

Santa Clara, California • Today

Full-time

Compensation information provided in the description

Formal Verification Engineer - #26-21752

U.S. Tech Solutions Inc.

Ben Lomond, California • 10d ago

Easy Apply

Contract

$80 - $85

Physical Design Engineer

Cystems Logic

Sunnyvale, California • 4d ago

Easy Apply

Contract, Third Party

Engineering Intern - Design Verification, Neural Engine (Spring 2027 Co-op)

Rivian

Palo Alto, California • Today

Full-time

USD 45.00 - 51.00 per hour

Hardware Design and Failure Analysis Engineer

Galaxy i Technologies, Inc.

San Jose, California • 11d ago

Contract, Third Party

Depends on Experience

2027 Masters Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 104,000.00 per year

2027 Undergrad Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 66,560.00 per year

Mechanical Design Engineer

TechSpace Solutions Inc.

Fremont, California • 6d ago

Easy Apply

Contract

Depends on Experience

Pre-Silicon Digital Verification Engineer

Apple, Inc.

Sunnyvale, California • Today

Full-time

Senior Debug Verification Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Principal Verification Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 230,000.00 per year

Verification Engineer 5

TPI Global (formerly Tech Providers, Inc.)

San Jose, California • Today

Full-time

CPU Formal Verification Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 147,900.00 - 221,900.00 per year

Design Validation Engineer

ATEM Corp

San Jose, California • 20d ago

Easy Apply

Full-time

Depends on Experience

Industrial Design Engineer 3

DGN Technologies

Sunnyvale, California • 4d ago

Easy Apply

Third Party, Contract

$103 - $103

Systems Design/Architecture Engineer 4

DGN Technologies

Sunnyvale, California • 4d ago

Easy Apply

Third Party, Contract

$115 - $115

Hardware Design & Failure Analysis Engineer

SysMind, LLC

San Jose, California • 6d ago

Easy Apply

Third Party, Contract

$66 - $70

Automation and Fixture Design Engineer

OSI Engineering, Inc.

Cupertino, California • 6d ago

Easy Apply

Contract

Depends on Experience

Physical Design Engineer

Comprehensive Resources Inc.

Sunnyvale, California • Today

Easy Apply

Full-time, Part-time, Contract, Third Party

DFT (Design for Test) Engineer (California, Texas) - W2 Only

Collaborate Solutions, Inc.

San Jose, California • 4d ago

Easy Apply

Full-time

$60 - $70

Physical Design Engineer

Indus Valley

Hybrid in San Jose, California • Today

Easy Apply

Third Party, Contract

Depends on Experience

Physical Design Engineer (Top-Level / Full-Chip) - AS

Central Business Solutions

San Jose, California • Today

Easy Apply

Full-time

Depends on Experience

Physical Design Engineer

FSTONE Technologies

Hybrid in Sunnyvale, California • Today

Easy Apply

Contract, Third Party

Depends on Experience

Hardware Systems Engineer - Board Design

Apple, Inc.

Cupertino, California • Today

Full-time

Job Details

Skills

SVA
RTL
SystemVerilog
Formal Verification

Summary

Role: GPU Formal Design Verification

Location: San Jose, CA (Onsite: M-F)

Duration: 6 Months Contract

Pay rate: $85-95/hr W2

Description:

Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequential equivalence for clock gating logic & so, verifying design features using assertions and verifying datapath equivalence of C and RTL models.
You will diagnose formal failures and work closely with RTL designers to update formal setup or RTL code.
GPU designs provide a wealth of technical challenges in memory hierarchy, parallel processing units, and complex mathematical units.
This is a challenging and rewarding position where you will learn cutting-edge design and verification techniques from an exceptionally talented team, and where your contributions will make a visible impact to the end product.
Develop formal verification setup using System Verilog modules and Assertions
Run formal verification checks, analyze the results, and debug any issues.
Develop and enhance constraints, checks, and cover points to achieve verification quality.
Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
Hands-on experience in developing formal based datapath verification setups using RTL & C Models
Hands-on experience in developing formal property-based feature verification setups
In-depth expertise on proof depth and convergence analysis for formal setups
Root cause formal failures to identify design or test setup issues.
Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions.
Work closely with cross-functional teams, including design, architecture, and software teams, to ensure that verification efforts are aligned with project goals and requirements.
Participate in the development and improvement of verification methodologies, tools, and flows to increase efficiency and effectiveness of verification efforts.
Adhere to project execution and planning approaches using Confluence, JIRA and relevant techniques.
Create and maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results.
Responsible in driving formal verification tasks & report to project verification leads as required

Skills And Qualifications:

BSEE, Computer Engineering, or Computer Science bachelor’s degree and a minimum of 3+ years of experience
Masters or Ph.D. degree preferred
Good understanding of CPU and/or GPU design architecture
Strong experience or exposure to System Verilog (SV) and System Verilog Assertion (SVA) coding skills is required
Experience in developing formal verification setups is a must
Experience in developing constrained random testbenches is preferred
Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal
Experience working in a Linux environment
Excellent communication skills and be able to work with cross-functional teams to execute verification plan

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91117675
Position Id: 9131890
Posted 17 hours ago

Fitment

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Contact the job poster

Ganesh Iyer

Recruiter @ NUBYT, INC.

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Formal Verification Engineer - #26-21752

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Duration: 12+ Months Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be

Easy Apply

Contract

$80 - $85

Job Details

Skills

SVA
RTL
SystemVerilog
Formal Verification

Summary

Role: GPU Formal Design Verification

Location: San Jose, CA (Onsite: M-F)

Duration: 6 Months Contract

Pay rate: $85-95/hr W2

Description:

Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequential equivalence for clock gating logic & so, verifying design features using assertions and verifying datapath equivalence of C and RTL models.
You will diagnose formal failures and work closely with RTL designers to update formal setup or RTL code.
GPU designs provide a wealth of technical challenges in memory hierarchy, parallel processing units, and complex mathematical units.
This is a challenging and rewarding position where you will learn cutting-edge design and verification techniques from an exceptionally talented team, and where your contributions will make a visible impact to the end product.
Develop formal verification setup using System Verilog modules and Assertions
Run formal verification checks, analyze the results, and debug any issues.
Develop and enhance constraints, checks, and cover points to achieve verification quality.
Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
Hands-on experience in developing formal based datapath verification setups using RTL & C Models
Hands-on experience in developing formal property-based feature verification setups
In-depth expertise on proof depth and convergence analysis for formal setups
Root cause formal failures to identify design or test setup issues.
Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions.
Work closely with cross-functional teams, including design, architecture, and software teams, to ensure that verification efforts are aligned with project goals and requirements.
Participate in the development and improvement of verification methodologies, tools, and flows to increase efficiency and effectiveness of verification efforts.
Adhere to project execution and planning approaches using Confluence, JIRA and relevant techniques.
Create and maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results.
Responsible in driving formal verification tasks & report to project verification leads as required

Skills And Qualifications:

BSEE, Computer Engineering, or Computer Science bachelor’s degree and a minimum of 3+ years of experience
Masters or Ph.D. degree preferred
Good understanding of CPU and/or GPU design architecture
Strong experience or exposure to System Verilog (SV) and System Verilog Assertion (SVA) coding skills is required
Experience in developing formal verification setups is a must
Experience in developing constrained random testbenches is preferred
Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal
Experience working in a Linux environment
Excellent communication skills and be able to work with cross-functional teams to execute verification plan

Dice Id: 91117675
Position Id: 9131890
Posted 17 hours ago

Fitment