Ganesh Iyer

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens