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Lead Software Engineer - Low Power Verification

Cadence Design Systems Inc

San Jose, California • Today

Full-time

USD 114,800.00 - 213,200.00 per year

Lead Software Engineer - Low-Power Verification

Cadence Design Systems Inc

San Jose, California • Today

Full-time

USD 114,800.00 - 213,200.00 per year

Lead IP Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Lead Power Methodology Analysis Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 203,000.00 per year

Lead Principal Platform Software Engineer

Oracle Corporation

Santa Clara, California • Today

Full-time

USD 96,800.00 per year

Lead Principal Data Systems Software Engineer

Oracle Corporation

Pleasanton, California • Today

Full-time

USD 122,800.00 - 306,400.00 per year

Lead ASIC Verification Engineer

General Dynamics

Remote or Boise, Idaho • Today

Full-time

USD 173,032.00 - 190,000.00 per year

Senior Lead Engineer, Software

Celestica International LP

San Jose, California • Today

Full-time

Senior Lead Engineer, Software - BMC

Celestica International LP

San Jose, California • Today

Full-time

Lead I&C (Instrumentation & Controls) Embedded Software Engineer

GE Vernova

Remote or Wilmington, North Carolina • Today

Full-time

USD 98,400.00 - 164,000.00 per year

Lead Software Development Engineer

UKG Careers

Remote • Today

Full-time

USD 133,900.00 - 190,750.00 per year

Lead Software Engineer - Remote

UnitedHealth Group

Remote or Eden Prairie, Minnesota • Today

Full-time

USD 112,700.00 - 193,200.00 per year

Tech Lead - Software Engineering

DataVisor

Mountain View, California • Today

Full-time

USD 170,000.00 - 220,000.00 per year

Sr. Engineer, Silicon Validation

Ayar Labs

San Jose, California • Today

Full-time

Lead Product Security Engineer

Cloud Software Group

San Ramon, California • Today

Full-time

USD 191,520.00 - 287,280.00 per year

Sr. Diagnostic Engineer, Low Voltage, Energy Distribution

Rivian

Hayward, California • Today

Full-time

USD 107,000.00 - 133,800.00 per year

Senior Staff Pre Silicon Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Sr. Staff Engineer - Processor Verification and Compiler Validation

Enphase Energy

Fremont, California • Today

Full-time

USD 135,000.00 - 205,200.00 per year

Senior DevOps Validation Engineer

Keeper Security, Inc.

Remote • Today

Full-time

Senior Hardware Validation Engineer

Wing

Palo Alto, California • Today

Full-time

USD 211,000.00 - 224,000.00 per year

Lead Embedded Systems Software Engineer

E-Space

Saratoga, California • Today

Full-time

USD 150,000.00 - 225,000.00 per year

Job Details

Skills

Cadence
Emulation
Prototyping
Usability
PowerPC
Pay Per Click Management
Reporting
Documentation
ROOT
Research and Development
Marketing Communications
RTL
Verilog
SystemVerilog
VHDL
Root Cause Analysis
Test Cases
C++
Object-Oriented Programming
Fluency
Evaluation
Artificial Intelligence
Communication
Technical Writing
Debugging
Workflow
Sales

Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.

As a Lead Software Engineer - Low Power Verification you will be responsible for improving the performance and usability of UPF debug features, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do:

Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
Scale UPF event logging and violation detection - apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs.
Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples.
Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).
Help consolidate and unify UPF debug across Palladium and Protium.

What we are looking for

BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
Strong debugging skills - root-cause analysis from logs, waveforms, traces, testcases, and user reports.
Ability to read, review, and reason about C++ code and object-oriented designs.
Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
Strong communication and technical writing skills - able to turn scattered debug evidence into clear, user-facing workflows.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: CADENCE
Position Id: 2cc31e177f3de1744630b356e98b194d
Posted 30+ days ago

Fitment

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San Jose, California

•

Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms. As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new I 1801 LRM revisions, and rebuilding UPF documentation around

Full-time

USD 114,800.00 - 213,200.00 per year

CPU Low Power RTL Design Engineer

Santa Clara, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, you will work with chip architects to conceive of the micro-architecture and help with architecture/product definition through early involvement in the product life cycle. Required for this Role: MS degree in Computer or Electrical Engineering or BS degree

Full-time

USD 124,300.00 - 186,500.00 per year

Principal Engineer, Hardware Emulation

San Jose, California

•

Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 219,000.00 - 351,000.00 per year

Staff Product Applications Engineer-Silicon Debug & Embedded Systems

San Jose, California

•

Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 140,840.00 per year

Job Details

Skills

Cadence
Emulation
Prototyping
Usability
PowerPC
Pay Per Click Management
Reporting
Documentation
ROOT
Research and Development
Marketing Communications
RTL
Verilog
SystemVerilog
VHDL
Root Cause Analysis
Test Cases
C++
Object-Oriented Programming
Fluency
Evaluation
Artificial Intelligence
Communication
Technical Writing
Debugging
Workflow
Sales

Summary

Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
Scale UPF event logging and violation detection - apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs.
Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples.
Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).
Help consolidate and unify UPF debug across Palladium and Protium.

What we are looking for

BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
Strong debugging skills - root-cause analysis from logs, waveforms, traces, testcases, and user reports.
Ability to read, review, and reason about C++ code and object-oriented designs.
Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
Strong communication and technical writing skills - able to turn scattered debug evidence into clear, user-facing workflows.

Dice Id: CADENCE
Position Id: 2cc31e177f3de1744630b356e98b194d
Posted 30+ days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

San Jose, California

•

Today

Full-time

USD 114,800.00 - 213,200.00 per year

CPU Low Power RTL Design Engineer

Santa Clara, California

•

Today

Full-time

USD 124,300.00 - 186,500.00 per year

Principal Engineer, Hardware Emulation

San Jose, California

•

Today

Full-time

USD 219,000.00 - 351,000.00 per year

Staff Product Applications Engineer-Silicon Debug & Embedded Systems

San Jose, California

•

Today

Full-time

USD 140,840.00 per year

Lead Software Engineer - Low Power Verification

Skills

Summary

Dice Job Match Score™

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Lead Software Engineer - Low Power Verification

Job Details

Skills

Summary

Dice Job Match Score™

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