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Design Verification Engineer – UVM/SystemVerilog

Avila IT

San Jose, California • 9d ago

Easy Apply

Contract

Depends on Experience

Design Verification Engineer

Kairos

San Jose, California • 7d ago

Easy Apply

Contract

Depends on Experience

Design Verification Engineer

SIGNin Solutions Inc.

San Jose, California • Yesterday

Easy Apply

Full-time, Third Party

Depends on Experience

Design Verification Engineer

NMK Global Inc.

San Jose, California • 6d ago

Easy Apply

Contract, Third Party

Depends on Experience

Principal Verification Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 230,000.00 per year

IP Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Verification Engineer 5

TPI Global (formerly Tech Providers, Inc.)

San Jose, California • Today

Full-time

ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

IC Verification Engineer

Broadcom Corporation

San Jose, California • Today

Full-time

USD 121,900.00 - 195,000.00 per year

Senior ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

Senior Debug Verification Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Lead IP Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Mixed Signal Verification Engineer

West Coast Consulting LLC

San Jose, California • Today

Contract

Senior Performance Verification Engineer - SoC

Microsoft Corporation

Mountain View, California • Today

Full-time

USD 119,800.00 - 234,700.00 per year

Low-Power & CDC Verification Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 103,600.00 per year

Senior Staff Pre Silicon Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Senior System Level Verification Engineer

Axiado

San Jose, California • Today

Full-time

Sr. Design Verification Engineer || San Jose, CA

McKinsol Consulting Inc

San Jose, California • Today

Easy Apply

Contract, Third Party

Depends on Experience

Systems Engineer - Verification Engineer

Katalyst Healthcares and Lifesciences

Pleasanton, California • 14d ago

Full-time

DV (Design Verification) Engineer (California, Texas) - W2 Only

Collaborate Solutions, Inc.

San Jose, California • Yesterday

Easy Apply

Full-time

$60 - $70

CPU Verification Engineer (RISC-V)

J VERS LLC

Santa Clara, California • Today

Full-time

USD 167,100.00 - 250,700.00 per year

ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV

Boeing Company

Mountain View, California • Today

Full-time

USD 164,900.00 - 223,100.00 per year

Sr. FPGA Verification Engineer

Reliable Robotics

Remote or Mountain View, California • Today

Full-time

USD 215,000.00 - 300,000.00 per year

ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead)

Boeing Company

Mountain View, California • Today

Full-time

USD 98,600.00 - 133,400.00 per year

RTL Verification Engineer # 26-21738

U.S. Tech Solutions Inc.

Ben Lomond, California • 6d ago

Easy Apply

Contract

$80 - $85

CPU Formal Verification Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 147,900.00 - 221,900.00 per year

CPU Verification ML Tool Engineer

Apple, Inc.

Santa Clara, California • Today

Full-time

Verification & Validation Engineer Multimodal AI

System Edge (USA) L.L.C.

Sunnyvale, California • 8d ago

Easy Apply

Full-time

Depends on Experience

Software Verification & Validation Engineer

PlusAI

Santa Clara, California • Today

Full-time

USD 110,000.00 - 140,000.00 per year

Senior Physical Verification CAD Engineer

Microsoft Corporation

Mountain View, California • Today

Full-time

USD 119,800.00 - 234,700.00 per year

Job Details

Skills

Design Verification
Design Verification Engineer
SystemVerilog
UVM
Functional Verification
IP Verification
PCIe
Ethernet
AXI
AMBA
ARM
ARC CPU
SoC Verification
IP Integration
VIP Integration
Functional Coverage
Coverage Closure
Constrained Random Verification
Testbench Development
RTL Debugging
Regression Testing
Verification Planning
Semiconductor
ASIC Verification
Hardware Verification.

Summary

Job Summary

We are seeking an experienced Design Verification (DV) Engineer to join our Interface IP Design Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog and UVM-based verification, along with expertise in validating complex IP subsystems and standard interface protocols. You will collaborate closely with architects, RTL designers, integration teams, and external IP vendors to ensure functional correctness, performance, and compliance with architectural specifications across the hardware-software stack.

Key Responsibilities

Own end-to-end design verification for one or more IP subsystems, including PCIe, Ethernet, ARM/ARC CPUs, low-power peripherals, and sensors.
Develop, maintain, and enhance reusable verification environments using SystemVerilog and UVM.
Understand vendor IP configurations, specifications, and integration requirements while coordinating with internal IP teams and external vendors.
Verify functional correctness, performance, protocol compliance, and corner-case scenarios.
Collaborate with SoC Design Verification and integration teams to ensure seamless integration of third-party IPs into the overall chip architecture.
Develop and execute verification plans, test scenarios, and regression suites.
Drive functional and code coverage closure, analyze verification gaps, and support final verification sign-off.
Debug complex failures, identify root causes, and work closely with RTL design and software teams to resolve issues.
Communicate verification progress, technical findings, risks, and recommendations to cross-functional stakeholders.

Required Qualifications

5+ years of hands-on experience in Design Verification Engineering.
Strong proficiency in SystemVerilog and UVM methodologies.
Experience developing scalable, reusable testbenches and constrained-random verification environments.
Familiarity with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPUs.
Experience with functional coverage, coverage analysis, regression testing, and verification sign-off.
Strong debugging, problem-solving, and analytical skills.
Ability to work independently, take ownership of verification tasks, and deliver results with minimal supervision.
Excellent communication and collaboration skills when working with design, architecture, integration, and software teams.

Preferred Qualifications

Experience working with external IP vendors and managing IP/VIP integration.
Hands-on experience with UVM-based verification and SystemVerilog testbench development.
Knowledge of SoC integration and hardware-software interaction.
Experience identifying corner-case bugs and debugging complex IP-level issues.
Ability to thrive in a fast-paced engineering environment and manage multiple verification priorities.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: RTX1ca0d4
Position Id: 9113699
Posted 9 days ago

Fitment

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Contact the job poster

Navya Amsha

Recruiter @ Avila IT

View Profile

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San Jose, California

•

Today

Sr. Design Verification Engineer Location: San Jose, CA ( Onsite ) Facet to face interview is a must after Video call. Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ab

Easy Apply

Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

•

6d ago

NMK Global Inc.is a global IT Services & Solutions company specializing in IT Staffing, Technology Consulting, Workforce Solutions, and Application Development Services. We help organizations build high-performing technology teams by connecting them with exceptional talent across a wide range of industries. Our expertise, industry knowledge, and consultative approach enable clients to achieve successful business outcomes while helping professionals advance their careers. Job Title: Design Ver

Easy Apply

Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

•

7d ago

Location : Bay area (San Jose) CA Onsite Duration : Long term Locals We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges

Easy Apply

Contract

Depends on Experience

Design Verification Engineer

San Jose, California

•

Yesterday

Client: Etched Design Verification Engineer 6 Openings Location: San Jose, CA & Austin, TX - onsite Please find the JD: Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ab

Easy Apply

Full-time, Third Party

Depends on Experience

Job Details

Skills

Design Verification
Design Verification Engineer
SystemVerilog
UVM
Functional Verification
IP Verification
PCIe
Ethernet
AXI
AMBA
ARM
ARC CPU
SoC Verification
IP Integration
VIP Integration
Functional Coverage
Coverage Closure
Constrained Random Verification
Testbench Development
RTL Debugging
Regression Testing
Verification Planning
Semiconductor
ASIC Verification
Hardware Verification.

Summary

Job Summary

Key Responsibilities

Own end-to-end design verification for one or more IP subsystems, including PCIe, Ethernet, ARM/ARC CPUs, low-power peripherals, and sensors.
Develop, maintain, and enhance reusable verification environments using SystemVerilog and UVM.
Understand vendor IP configurations, specifications, and integration requirements while coordinating with internal IP teams and external vendors.
Verify functional correctness, performance, protocol compliance, and corner-case scenarios.
Collaborate with SoC Design Verification and integration teams to ensure seamless integration of third-party IPs into the overall chip architecture.
Develop and execute verification plans, test scenarios, and regression suites.
Drive functional and code coverage closure, analyze verification gaps, and support final verification sign-off.
Debug complex failures, identify root causes, and work closely with RTL design and software teams to resolve issues.
Communicate verification progress, technical findings, risks, and recommendations to cross-functional stakeholders.

Required Qualifications

5+ years of hands-on experience in Design Verification Engineering.
Strong proficiency in SystemVerilog and UVM methodologies.
Experience developing scalable, reusable testbenches and constrained-random verification environments.
Familiarity with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPUs.
Experience with functional coverage, coverage analysis, regression testing, and verification sign-off.
Strong debugging, problem-solving, and analytical skills.
Ability to work independently, take ownership of verification tasks, and deliver results with minimal supervision.
Excellent communication and collaboration skills when working with design, architecture, integration, and software teams.

Preferred Qualifications

Experience working with external IP vendors and managing IP/VIP integration.
Hands-on experience with UVM-based verification and SystemVerilog testbench development.
Knowledge of SoC integration and hardware-software interaction.
Experience identifying corner-case bugs and debugging complex IP-level issues.
Ability to thrive in a fast-paced engineering environment and manage multiple verification priorities.

Dice Id: RTX1ca0d4
Position Id: 9113699
Posted 9 days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Contact the job poster

Navya Amsha

Recruiter @ Avila IT

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

San Jose, California

•

Today

Easy Apply

Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

•

6d ago

Easy Apply

Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

•

7d ago

Easy Apply

Contract

Depends on Experience

Design Verification Engineer

San Jose, California

•

Yesterday

Easy Apply

Full-time, Third Party

Depends on Experience

Design Verification Engineer – UVM/SystemVerilog

Skills

Summary

Job Summary

Key Responsibilities

Required Qualifications

Preferred Qualifications

Dice Job Match Score™

Navya Amsha

Similar Jobs

Design Verification Engineer – UVM/SystemVerilog

Job Details

Skills

Summary

Job Summary

Key Responsibilities

Required Qualifications

Preferred Qualifications

Dice Job Match Score™

Navya Amsha

Similar Jobs