Senior Design Verification Engineer

Pay Type: W2 & C2C
Pay Range (USD):  $60/hr. W2 - $65/hr. W2
                                 $75/hr. C2C - $80/hr. C2C

Job Description *
Key Responsibilities & What You'll Be Doing:
•    Testbench Architecture & Development: Develop and maintain scalable, robust verification environments from scratch using SystemVerilog and UVM (including drivers, monitors, scoreboards, and virtual sequences). 
•    IP & Subsystem Verification: Verify high-performance and complex IP blocks, including AXI interconnects, NoCs (Network-on-Chip), crossbars, DMAs, compute arrays, and high-speed memory/networking subsystems. 
•    Protocol Verification: Execute rigorous protocol verification across target interfaces such as PCIe, Ethernet, HBM, or UCIe switches. 
•    Firmware & C-Test Integration: Collaborate closely with design and embedded software teams using ARM/RISC-V CPU architectures alongside C/C++ testbenches and test firmware. 
•    Regression Management & Triage: Execute automated regression test suites, rapidly triage simulation failures, isolate root causes (RTL bugs vs. testbench issues), and write assertions/assumptions/cover properties. 
•    Coverage Closure: Drive functional and code coverage closure to sign-off standards, identifying coverage holes and implementing targeted scenarios. 
•    Scripting & Automation: Build and modify scripts using Make, Perl, and Python to streamline build flows, automation pipelines, and log parsing. 
•    Customer Representation & Delivery: Ensure high standards of customer satisfaction by providing reliable, regular daily/weekly progress updates and managing technical execution. 

Required Qualifications & Technical Skills:
•    Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related technical discipline. 
•    Experience: Minimum of 8+ years of hands-on professional experience in ASIC design verification. 
•    Core Language & Methodology:
o    Advanced mastery of SystemVerilog (SV) and Universal Verification Methodology (UVM).
o    Proficiency in C/C++ for embedded testbenches or co-verification. 
•    Interconnect & Bus Protocols: Deep understanding of AMBA AXI/AHB protocols, NoC (Network-on-Chip) routing, and crossbar arbitration. 
•    Protocol Exposure: Hands-on verification experience with at least one major high-speed standard: PCIe, Ethernet, or HBM / UCIe. 
•    Verification Closure: Proven track record in writing verification plans, building constrained-random environments, debugging waveforms, and achieving 100% coverage closure. 
•    Automation Tools: Solid scripting capabilities in Python, Perl, and Makefiles within Linux environments. 
Operational Fit: High degree of independence ("startup mode"), capable of stepping into active execution cycles with minimal documentation or ramp-up time.

Applied Skills:
•    SystemVerilog
•    Universal Verification Methodology (UVM)
•    ASIC Design Verification
•    SoC Verification
•    AMBA AXI Protocol
•    Network-on-Chip (NoC)
•    PCIe
•    Ethernet
•    Functional Coverage
•    Constrained-Random Verification.