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Position :Principal/Lead Design Engineer Memory Controller (CHI-G / DFI) Location :San Jose, CA Experience :10+ yearsRole SummaryWe are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protocol and DDR/LPDDR/HBM PHY-facing DFI (DFI Interface). This role owns modifying and extending an existing memory controller design to accommodate new architectura
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