Verification Lead / Principal Verification Engineer – PCIe Gen5/Gen6

Position :Verification Lead Memory Controller (CHI-G / DFI) Location :San Jose, CA Experience :10+ years Role Summary We are seeking a Verification Lead to own the verification strategy, planning, and execution for the Memory Controller subsystem, including CHI-G protocol compliance and DFI interface verification. This role will lead a team of verification engineers through architecture updates driven by design changes to the memory controller, ensuring full functional coverage and sign-off q

Position :Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration Location :San Jose, CA Experience :10+ years Job Summary We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely

Position :Principal/Lead Design Engineer Memory Controller (CHI-G / DFI) Location :San Jose, CA Experience :10+ years Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protocol and DDR/LPDDR/HBM PHY-facing DFI (DFI Interface). This role owns modifying and extending an existing memory controller design to accommodate new architec