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Principal / Lead Engineer – PCIe Gen5/Gen6 Controller, PHY & SerDes Integration

San Jose, CA, US • Posted 7 hours ago • Updated 7 hours ago

Contract W2

Contract Corp To Corp

Contract Independent

24 Months

No Travel Required

On-site

Depends on Experience

Goldenpick Technologies LLC

Fitment

Dice Job Match Score™

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Job Details

Skills

PCIe
Gen5
Gen6
PHY
SerDes

Summary

Position : Principal / Lead Engineer – PCIe Gen5/Gen6 Controller, PHY & SerDes Integration
Location :San Jose, CA
Experience :10+ years

Job Summary
We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with Architecture, RTL, Verification, DFT, Physical Design, STA, and Silicon Validation teams.
The ideal candidate should possess deep expertise in PCIe protocol, high-speed interfaces, subsystem integration, timing closure methodologies, and full ASIC development flow from architecture through silicon bring-up.

Key Responsibilities

Lead development and integration of PCIe Gen5/Gen6 Controller, PHY, and SerDes subsystems.
Define subsystem architecture, interface specifications, microarchitecture, and design documentation.
Participate in Transaction Layer development and enhancements.
Support PCIe/CXL interoperability and advanced features.
Drive integration of high-speed PHY and SerDes IPs.

Work on:

Link training
Equalization
PLL integration
Reference clock architecture
PIPE interfaces
Lane repair and lane aggregation
Collaborate with analog and PHY teams during integration and debug.

Work closely with DV teams to:

Define comprehensive verification plans.
Review UVM-based test environments.
Develop assertions and coverage metrics.
Support protocol compliance testing.
Debug simulation, emulation, FPGA, and post-silicon issues.

Support DFT implementation including:

Scan insertion
MBIST
LBIST
JTAG/Boundary Scan
At-speed testing
Define test requirements for PCIe controller and PHY subsystems.
Collaborate with DFT and silicon validation teams to achieve coverage target
Develop and maintain subsystem-level SDC constraints for:
Synthesis
Static Timing Analysis
Place & Route
Timing signoff
Work with PD and STA teams to achieve timing closure.
Silicon Bring-Up & Debug

Support:

PCIe link training debug
Compliance testing
Silicon characterization
Performance tuning
Analyze protocol traces and lab debug logs.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91164342
Position Id: 936-36890-1787348885
Posted 7 hours ago

Company Info

About Goldenpick Technologies LLC

GoldenPick Technologies is a cutting-edge career search and leadership hiring firm that leverages innovative recruitment solutions to deliver exceptional talent. With over 20 years of industry expertise, we provide our clients with a high-caliber resource pool through our intelligent search and selection process. Our robust internal processes ensure precise candidate matching for current and future requirements. We prioritize client satisfaction, delivering prompt solutions with diligence, continuous feedback, and personal accountability.

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Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location :San Jose, CA Experience :10+ years Position Summary We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transcation Layer, Controller, PHY and Serdes. The candidate will be responsible for verification planning, methodology definition, UVM environment architecture, coverage closure, protocol compliance verification, and leadership of a team of veri

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