
Marvell Semiconductor Inc.
Santa Clara, California • Today
Full-time
USD 150,680.00 - 225,700.00 per year
24 results (1 new)

Marvell Semiconductor Inc.
Santa Clara, California • Today
Full-time
USD 150,680.00 - 225,700.00 per year

Samsung Electronics America
San Jose, California • Today
Full-time
USD 163,000.00 - 253,000.00 per year


Marvell Semiconductor Inc.
Santa Clara, California • Today
Full-time
USD 150,680.00 - 225,700.00 per year






M/A-COM Technology Solutions Inc
Milpitas, California • Today
Full-time
USD 149,000.00 - 212,000.00 per year







Cushman & Wakefield
Remote or Nashville, Tennessee • Today
Full-time
USD 157,250.00 - 185,000.00 per year




Samsung Electronics America
San Jose, California • Today
Full-time
USD 163,000.00 - 253,000.00 per year

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Sunnyvale, California
•
Today
Do you want to help build future generations of processors that will enable the next remarkable Apple innovation? If so, we invite you to consider joining our team. We are seeking an engineer with a passion for hardware and strong CAD flow development and collaboration skills. You will develop, maintain, and enhance AMS (Analog/Mixed-Signal) simulation methodology and tools for our analog, RF, interconnect, PMIC, and memory design teams. You will gain hands-on experience in circuit analysis, pre
Full-time
San Jose, California
•
Today
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t
Full-time
USD 185,000.00 - 240,000.00 per year
San Jose, California
•
Today
Job Title: Analog Layout Engineer (592074) Location: San Jose, CA (Onsite) Description As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner. Layout of sensitive active / passive components including resistors, capacitors and inductors. Design verification including DRC, LVS, ERC and ANT and extraction. Block level floor planning with design engineers. R
Full-time
San Jose, California
•
Today
Principal Engineer, SerDes AMS Design and Architecture Location: San Jose, CA (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world's leading semiconduct
Full-time
USD 224,000.00 - 308,000.00 per year