Company:Qualcomm Atheros, Inc.
Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs.
Responsibilities: Qualcomm's Connectivity SoC organization is seeking candidates for physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
- Tasks also involve the tiles level development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals.
- Additional responsibilities in this role involves the experience of
- functional and test (DFT) mode constraints for place and route,
- floorplanning, power planning
- IR drop analysis
- routing, timing optimization and closure
- implementing timing fixes and functional ECOs
- debugging and fixing physical violations and formal verification.
- The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell.
- This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
Required Skill/experience:
2+ years industry experience in the following areas
- Tiles level or sub-system level or SoC top level physical design successful tapeout experience
- Floorplanning of macro cells
- Place & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
- Timing closure (STA) experience in Synopsys PTSI
- Function ECO implementation
- Formal verification (FV) experience
- Power domain analysis (IR Drop/PDN) experience
- Physical verification (PV) experience
Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
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Pay range and Other Compensation & Benefits: $134,500.00 - $201,700.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
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