Immediate need for a talented PD Engineer. This is a 06+ Months Contract opportunity with long-term potential and is located in San Jose, CA (Remote). Please review the job description below and contact me ASAP if you are interested.
Job ID:26-27753
Pay Range: $68 - $70/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Key Responsibilities:
- Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
- Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
- Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
- Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
- Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
- Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.
Key Requirements and Technology Experience:
- Bachelor s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
- 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
- Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
- 7+ years of experience in physical design roles and related activities.
- Proven ability to adhere to tight schedules and implement low-power design techniques.
- Experience in System-on-Chip (SoC) design and implementation.
- Expertise in sub-7nm node technologies.
- Familiarity with industry-standard EDA tools and their capabilities.
- Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
Our client is a leading IT Industry and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.
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