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Physical Design
VLSI
Chip
PDE

Summary

Hi,

Role: Physical Design Engineer
Location: Santa Clara, CA
Work mode: 5 Days Onsite

Fulltime and W2 contracts
Any Visa is workable

Total 10 positions available, covering all experience levels from Junior to Senior.

*Experience:* 4 15 Years

Key Responsibilities
* Execute end-to-end physical design implementation including:
* Floorplanning
* Power grid design
* Placement & Routing
* Clock Tree Synthesis (CTS)
* Timing Closure
* Signal/Power Integrity Signoff
* Physical Verification (DRC/LVS/Antenna)
* EM/IR Analysis
* DFM Closure
* Perform full-chip and block-level timing analysis and provide optimization guidance to subsystem/block owners.
* Work on advanced low-power and high-performance SoC designs.
* Drive design convergence and signoff closure across multiple implementation stages.
* Collaborate with cross-functional teams including RTL, STA, DFT, and Signoff.

Required Skills
* Strong hands-on experience with Cadence and Synopsys EDA tool suites.
* Expertise in STA and timing signoff using Synopsys PrimeTime.
* Experience handling large block/subsystem/full-chip implementation.
* Strong scripting knowledge in TCL, Perl, Shell, and Make flows.
* Good understanding of advanced technology nodes including 7nm/5nm/3nm.
* Strong debugging, analytical, and communication skills.
* Self-driven and capable of driving new methodologies and automation.

Qualifications

Bachelor's or Master's degree in Electronics / VLSI / Electrical Engineering.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91126316
Position Id: 2026-23730
Posted 1 day ago

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Hiring - Physical Design Engineer in Santa Clara, CA

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Hiring - Physical Design Engineer in Santa Clara, CA

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