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POSITION: Senior DV Engineer Location - San Jose, CA, USA Contract :12+ months Experience: 10+ years The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, perip
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