Design Verification (DV) Engineer

POSITION: Senior DV Engineer Location - San Jose, CA, USA Contract :12+ months Experience: 10+ years The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, perip

Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s

We have opening for Design Verification Engineer, Principal Location - Santa Clara, CA Full time permanent position Sponsorship available Must-haves BS Computer Engineering, Electrical Engineering, or Computer Science 10+ years of verification and firmware and software development experience (or MS/PhD 5+ years experience). Proven track records of leading Design Verification implementation activity Tape-out of complex SOC under tight schedule. In depth understanding and experience with System V

Principal Engineer, Digital Verification & Emulation Location: San Jose, CA - on-site Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics, or CPO, we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders including NVIDIA, AMD, MediaTek and Intel, and manufactured in partnership with the world's leading semi