Low Power Design Engineer

Job Description: Low Power Design Engineer 

Experience: 4+ years in VLSI / Semiconductor Design

Employment Type: Contract (via vendor)

About the Role

We are looking for a Low Power Design Engineer to join the Silicon SOC team. The role focuses on power analysis, RTL power estimation, and power optimization for next-generation wearable and AR/VR SoC designs. You will work on power-critical flows that directly impact battery life and thermal performance of our products.

Mandatory Requirements

1. Power Analysis Tool Experience (MUST HAVE)

At least 1 year of most recent experience in one of the following:

Priority              Tool      Vendor

Preferred         Synopsys PrimePower / PTPX             Synopsys

Acceptable     Ansys PowerArtist      Ansys

Acceptable     Cadence Voltus          Cadence

Candidates with PrimePower/PTPX experience will be given first priority.

2. RTL Power Estimation (MUST HAVE — at least one)

3. Power Replay Methodology

4. Minimum Experience

Key Responsibilities

Preferred / Nice-to-Have Skills

Ideal Candidate Profile

Screening Priority

Priority              Criteria

P1 — Interview immediately       PrimePower/PTPX + PP-RTL/RTL-A + Power Replay (all three)

P2 — Strong consider      PrimePower/PTPX + at least one of PP-RTL or Power Replay

P3 — Review carefully     PowerArtist or Voltus (no PrimePower) + 5+ yrs low-power experience

P4 — Pass              No power analysis tool experience, or only PD/STA/verification background

Notes for Vendors

Please include specific tool names and years of experience in the resume summary.

Profiles with only VCLP/CLP clock-tree power or power-grid IR-drop analysis are not a match.

Recent experience matters — candidates must have used PrimePower, PowerArtist, or Voltus within the last 1 year in their current or most recent role.

Do NOT send candidates whose experience is limited to Physical Design (PnR), STA, or Formal/LEC verification — even if they mention "low power" in passing.

Comfortable with automation and scripting to improve flow efficiency

Understands the full power analysis pipeline: RTL estimation → gate-level analysis → power replay → sign-off

Can independently set up and run PrimePower/PTPX flows

Has worked on power sign-off for complex SoCs at companies like Synopsys, Intel, Qualcomm, Broadcom, Samsung, or similar

Familiarity with Siemens Power-Pro

Experience with mobile, wearable, or AR/VR class SoCs

Power gating, clock gating, DVFS strategy experience

SoC-level power architecture and multi-voltage domain experience

Python/Tcl scripting for EDA flow automation

Zebu-Empower or emulation-based power analysis

UPF/CPF power intent specification and verification

Generate power reports and drive power sign-off for tape-out milestones

Identify power reduction opportunities (clock gating, power gating, voltage scaling)

Collaborate with design, verification, and architecture teams on power budgeting

Develop and optimize low-power automation flows (scripts, methodologies)

Run power replay simulations to validate power estimates against real workloads

Perform gate-level and RTL-level power analysis using PrimePower/PTPX or equivalent tools

1+ year of most recent experience must be on power analysis tools (PrimePower preferred)

4+ years total in VLSI / semiconductor low-power design

Experience with simulation or emulation-based power replay analysis

Cadence Joules (acceptable equivalent)

Synopsys PrimePower-RTL (PP-RTL) / RTL Architect (RTL-A) (preferred)