"Exciting Opportunity! We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA! Key Responsibilities: - Low power design and verification (UPF, VCLP) - Power analysis and optimization (PTPX) - STA and timing analysis - Synthesis and physical design (DC synthesis) Requirements: - 5+ years of experience in ASIC design, low power design, and verification - Proficiency in scripting languages (Shell, TCL, Perl, Python) - Experience with VCLP, PTPX, Formality,

Company Description Our Mission At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we're looking for innovators who are as committed to shaping the future of cybersecurity as we are. Who We Are We take our mission of

Job Description Permanent Residents and Visa-holders are not eligible for employment. General Summary This full-time position is in the Systems Development Department of Kratos SRE and is a highly motivated and self-driven role that will focus on leading development efforts for next-generation technologies for microelectronics Key Responsibilities Provide technical leadership in the development and evaluation of custom integrated circuit designs for defense applications,Investigate, research

Hi, Hope you are doing good Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete onsite) locals highly preferred Duration: 6-12 months Experience: 8+ years (Relevant) A bachelor's degree in electrical or computer engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a master's degree in electrical or computer engineering with at least 8 years of experience in ASIC or a related discipline. A comprehensive understanding of FPGA design,

Job Title: ASIC STA & CAD Engineering Location: Longmont, Colorado (Hybrid) Duration: Long Term Contract Domain: Engineering Key Responsibilities: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to understand the design

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth. CONTRACT Position: 12 Months Location: Onsite in Orlando, FL Candidate must be authorized to work in the US We are seeking a highly skilled ASIC & FPGA Design Engineer to join o

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband in

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadban

Work Shift: 1st Shift (9/80A) Looking for an ASIC engineer to validate the performance of a high speed ASIC at our Aviation Blvd facility in Baltimore, MD. The ASIC is tested using a Stratix 10 FPGA and requires that the qualified candidate have experience of writing Matlab code and VHDL to generate commands to control and capture results. Familiarity with operation of High Speed Interfaces like a SerDes is required. Responsibilities: Conduct testing of ASIC in the lab utilizing the FPGA which i

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadban

Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Colla

Position: Senior ASIC Design Engineer Emulation(HAPS Engineer) Location: San Jose, CA (Complete onsite) locals highly preferred Interview: video Duration: 6-12 months Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodolog

What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the S

Job Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100% Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimizationDefine power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technologyRun pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology

Job Title : Advanced ASIC / FPGA Embedded Engineer Location: Middletown, RI Wage Range: 60-67 Job Number: 25-02803 Job Description: Our client, a large defense contractor, has an immediate opening for an Advanced ASIC / FPGA Embedded Engineer to work from their Middletown, RI facility. As an Advanced ASIC / FPGA Embedded Engineer, you'll be a member of or lead a cross functional team dedicated to the development of military-grade electronics and underwater acoustic systems. Qualifications:

WORK SHIFT: 1st Shift (9/80A) Pay Range:$90 - $100/hr. The pay rate may differ depending on your skills, education, experience, and other qualifications. Featured Benefits: Medical Insurance in compliance with the ACA.401(k).Sick leave in compliance with applicable state, federal, and local laws.Job Description: Looking for an ASIC engineer to validate the performance of a high speed ASIC at our Aviation Blvd facility in Baltimore, MD. The ASIC is tested using a Stratix 10 FPGA and requires that

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI's 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA. Perform digital hardware design in a fast-movin

Location: Orlando, FL Description: Role - Asic & Fpga Design Engineering Type: Contract Location - ( Onsite) Job Description: Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses spe

Job Description Job Title: FPGA/ASIC Design Specialist Working Pattern: Full-time Working location: Indianapolis, IN Rolls-Royce is looking for a FPGA/ASIC (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challenges in the industry while being part of a global, mu

Our client is a glbal infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications. They are urgently seeking a Sr. level Digital Signal Processing (DSP) R&D Engineer to join their growing team. Responsibilities include: Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and