Job#: 3051913 Job Description: Core Engineering - Design Engineer II
Location: Burlingame, California (Remote)
COMPENSATION: $113 - $123 HOURLY
Role Overview
We are seeking a digital design engineer to own the integration of the camera ingest path, including MIPI C/D-PHY and CSI-2 receivers, into the image signal processing (ISP) pipeline. This role involves developing the necessary glue logic to bridge CSI-2 and ISP interfaces and contributing to the overall subsystem architecture.
Key Responsibilities
- Integrate MIPI C-PHY/D-PHY, CSI-2 controller, and ISP IPs at the subsystem and chip level.
- Design and code glue logic for stream/virtual-channel handling, data-type unpacking, pixel packing/width conversion, and clock-domain crossing.
- Develop and maintain subsystem Architecture and top-level RTL, defining register maps and control paths.
- Drive subsystem/chip-level integration and contribute to the development of the verification plan.
- Extend and maintain Python-based integration and generation tooling.
- Support RTL-to-GDS processes, including constraints, synthesis, timing closure, and low-power intent for the camera subsystem.
- Work with FPGA engineers for early prototyping and with validation teams for bring-up and test program support.
- Support the hand-off and integration of blocks into the larger SoC environment.
Required Qualifications
Education: A Bachelor's degree in Electrical/Computer Engineering, Computer Science, or equivalent experience is required.
Experience: A minimum of 4 years of experience as a Digital Design Engineer, with ownership of SoC/subsystem integration, is necessary.
Technical Skills:- Hands-on experience with MIPI C-PHY and/or D-PHY, CSI-2 protocol, and camera ISP pipelines.
- Strong Verilog/SystemVerilog RTL coding and digital Architecture definition skills.
- Demonstrated ability to write new glue/bridge RTL, not solely integration.
- Proficiency in Python scripting.
- Familiarity with Tcl scripting, synthesis, and static timing.
- Experience with UPF-based simulation/low-power flows.
- Exposure to SystemVerilog UVM/OVM.
- Knowledge of cameras and experience working in that field.
- Familiarity with AI-assisted code.
Preferred Qualifications
- Experience with MIPI DSI/display, PCIe, USB, or other high-speed interfaces.
- Understanding of ISP algorithm/pipeline analysis and fixed-point data-paths.
- Experience with PHY/controller IP vendor deliverable bring-up and debug.
- Knowledge of DFT/testability and test-program definition; Power-Aware GLS.
- Experience with FPGA prototyping or Tensilica DSP/TIE.
- An MSEE/CS is preferred.
Everforth Apex is a world-class IT services company that serves thousands of clients across the globe. When you join Everforth Apex, you become part of a team that values innovation, collaboration, and continuous learning. We offer quality career resources, training, certifications, development opportunities, and a comprehensive benefits package. Our commitment to excellence is reflected in many awards, including ClearlyRateds Best of Staffing in Talent Satisfaction in the United States and Great Place to Work in the United Kingdom and Mexico.
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